ADF4217L/ADF4218L/ADF4219L
PIN FUNCTION DESCRIPTIONS
Mnemonic
DD1
Function
V
Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as
close as possible to this pin. VDD1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same
potential as VDD2.
VP1
Power Supply for the RF Charge Pump. This should be greater than or equal to VDD.
CPRF
Output from the RF Charge Pump. When enabled, this provides ICP to the external loop filter, which in turn
drives the external VCO.
DGNDRF
RFINA
Ground Pin for the RF Digital Circuitry
Input to the RF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
RFINB
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF.
AGNDRF
REFIN
Ground Pin for the RF Analog Circuitry
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled.
DGNDIF
Ground Pin for the IF Digital, Interface, and Control Circuitry
MUXOUT
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, or the scaled Reference Frequency to
be accessed externally (Table V).
CLK
DATA
LE
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches; the latch is selected using the control bits.
AGNDIF
NC
Ground Pin for the IF Analog Circuitry
This pin is not connected internally (ADF4219L only).
IFINB
Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass
capacitor, typically 100 pF (ADF4217L/ADF4218L only).
IFINA
DGNDIF
CPIF
Input to the IF Prescaler. This low level input signal is normally ac-coupled to the external VCO.
Ground Pin for the IF Digital, Interface, and Control Circuitry
Output from the IF Charge Pump. When enabled, this provides ICP to the external loop filter, which in turn drives
the external VCO.
VP2
Power Supply for the IF Charge Pump. This should be greater than or equal to VDD.
V
DD2
Positive Power Supply for the IF Interface and Oscillator Sections. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V.
VDD2 must have the same potential as VDD1.
–6–
REV. C
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