Datasheet > ADF4169WCCPZ-RL7

ADF4169WCCPZ-RL7

更新时间： 2022-02-26 11:09:36

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
36页	675K
描述
Direct Modulation/Fast Waveform Generating, Fractional-N Frequency Synthesizer

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ADF4169WCCPZ-RL7 数据手册

ADF4169

Data Sheet

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

Normalized Phase Noise Floor³

Phase-locked loop (PLL) bandwidth (BW) =

1 MHz

Integer-N Mode

Fractional-N Mode

Normalized 1/f Noise (PN_{1_f})⁴

−224

−217

−120

dBc/Hz

FRAC = 0; see Σ-Δ Modulator Mode section

Measured at 10 kHz offset, normalized

to 1 GHz

At the voltage controlled oscillator (VCO)

output

Phase Noise Performance⁵

12,002 MHz Output⁶

−96

dBc/Hz

At 50 kHz offset, 100 MHz PFD frequency

¹Operating temperature: −40°C to +125°C.

²Guaranteed by design. Sample tested to ensure compliance.

³This specification can be used to calculate phase noise for any application. Use the formula ((Normalized Phase Noise Floor) + 10 log(f_PFD) + 20 logN) to calculate

in-band phase noise performance as seen at the VCO output.

⁴The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (f_RF

and at an offset frequency (f) is given by PN = PN_{1_f}+ 10 log(10 kHz/f) + 20 log(f_RF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in

ADIsimPLL™.

)

⁵The phase noise performance is measured with a modified EV-ADF4159EB3Z evaluation board and the Rohde & Schwarz® FSUP signal source analyzer.

⁶f_REFIN= 100 MHz, f_PFD= 100 MHz, offset frequency = 50 kHz, RF_OUT= 12,002 MHz, N = 120.02, and loop bandwidth = 250 kHz.

TIMING SPECIFICATIONS

AV_DD= V_P= 2.7 V to 3.45 V, DV_DD= SDV_DD= 1.9 V, AGND = DGND = SDGND = CPGND = 0 V, T_A= T_MINto T_MAX, dBm referred to 50 Ω,

unless otherwise noted.

Table 2. Write Timing

Parameter

Limit at T_MINto T_MAX

Unit

Description

t₁

t₂

t₃

t₄

t₅

t₆

t₇

ns min

LE setup time

DATA to CLK setup time

DATA to CLK hold time

CLK high duration

CLK low duration

CLK to LE setup time

LE pulse width

Write Timing Diagram

t₄

t₅

CLK

t₂

t₃

DB2

(CONTROL BIT C3)

DB1

DB0 (LSB)

(CONTRO BIT C1)

DB30

DATA

DB31 (MSB)

(CONTROL BIT C2)

t₇

t₁

t₆

Figure 2. Write Timing Diagram

Rev. 0 | Page 4 of 36

1 2 345 6 7...36

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