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ADF4001BCP

更新时间: 2024-11-19 22:05:19
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
16页 189K
描述
200 MHz Clock Generator PLL

ADF4001BCP 数据手册

 浏览型号ADF4001BCP的Datasheet PDF文件第2页浏览型号ADF4001BCP的Datasheet PDF文件第3页浏览型号ADF4001BCP的Datasheet PDF文件第4页浏览型号ADF4001BCP的Datasheet PDF文件第5页浏览型号ADF4001BCP的Datasheet PDF文件第6页浏览型号ADF4001BCP的Datasheet PDF文件第7页 
a
200 MHz Clock Generator PLL  
ADF4001  
FEATURES  
GENERAL DESCRIPTION  
200 MHz Bandwidth  
The ADF4001 clock generator can be used to implement clock  
sources for PLLs that require very low noise, stable refer-  
ence signals. It consists of a low-noise digital PFD (Phase  
Frequency Detector), a precision charge pump, a programmable  
reference divider, and a programmable 13-bit N counter. In  
addition, the 14-bit reference counter (R Counter) allows  
selectable REFIN frequencies at the PFD input. A complete  
PLL (Phase-Locked Loop) can be implemented if the synthesizer  
is used with an external loop filter and VCO (Voltage Controlled  
Oscillator) or VCXO (Voltage Controlled Crystal Oscillator).  
The N min value of 1 allows flexibility in clock generation.  
2.7 V to 5.5 V Power Supply  
Separate Charge Pump Supply (VP) Allows Extended  
Tuning Voltage in 5 V Systems  
Programmable Charge Pump Currents  
3-Wire Serial Interface  
Hardware and Software Power-Down Mode  
Analog and Digital Lock Detect  
Hardware-Compatible to the ADF4110/ADF4111/  
ADF4112/ADF4113  
Typical Operating Current 4.5 mA  
Ultralow Phase Noise  
16-Lead TSSOP  
20-Lead Chip Scale Package  
APPLICATIONS  
Clock Generation  
Low Frequency PLLs  
Low Jitter Clock Source  
Clock Smoothing  
Frequency Translation  
SONET, ATM, ADM, DSLAM, SDM  
FUNCTIONAL BLOCK DIAGRAM  
AV  
DV  
DD  
V
R
SET  
CPGND  
DD  
P
REFERENCE  
ADF4001  
14-BIT  
R COUNTER  
REF  
IN  
PHASE  
FREQUENCY  
DETECTOR  
CP  
CHARGE  
PUMP  
14  
R COUNTER  
LATCH  
CURRENT  
SETTING 2  
CURRENT  
SETTING 1  
LOCK DETECT  
CLK  
FUNCTION  
LATCH  
24-BIT  
INPUT REGISTER  
DATA  
LE  
22  
CPI3 CPI2 CPI1 CPI6  
CPI5  
CPI4  
SD  
OUT  
N COUNTER  
LATCH  
HIGH Z  
AV  
DD  
13  
MUXOUT  
MUX  
M2  
RF  
RF  
A
IN  
13-BIT  
N COUNTER  
SD  
OUT  
B
IN  
M1  
M3  
CE  
AGND  
DGND  
REV. 0  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2001  

ADF4001BCP 替代型号

型号 品牌 替代类型 描述 数据表
ADF4001BCPZ-RL7 ADI

完全替代

200 MHz Clock Generator PLL
ADF4001BCPZ-RL ADI

完全替代

200 MHz Clock Generator PLL

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