Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Table 48. MMODE Register (Address 0xE700)
Bits
Bit Name
Default Value
Description
[1:0]
PERSEL[1:0]
00
00: Phase A selected as the source of the voltage line period measurement.
01: Phase B selected as the source of the voltage line period measurement.
10: Phase C selected as the source of the voltage line period measurement.
11: reserved. When set, the ADE7854A/ADE7858A/ADE7868A/ADE7878A mimic the
behavior of PERSEL[1:0] = 00.
2
PEAKSEL[0]
1
PEAKSEL[2:0] bits can all be set to 1 simultaneously to allow peak detection on all three
phases simultaneously. If more than one PEAKSEL[2:0] bit is set to 1, the peak measurement
period indicated in the PEAKCYC register decreases accordingly because zero crossings are
detected on more than one phase.
Setting this bit to 1 selects Phase A for the voltage and current peak registers.
Setting this bit to 1 selects Phase B for the voltage and current peak registers.
Setting this bit to 1 selects Phase C for the voltage and current peak registers.
Reserved. These bits do not manage any functionality.
3
PEAKSEL[1]
PEAKSEL[2]
Reserved
1
4
1
[7:5]
000
Table 49. ACCMODE Register (Address 0xE701)
Default
Value
Bits Bit Name
Description
[1:0] WATTACC[1:0] 00
00: signed accumulation mode of the total and fundamental active powers. Fundamental active
powers are available in the ADE7878A only.
01: reserved. When set, the device mimics the behavior of WATTACC[1:0] = 00.
10: reserved. When set, the device mimics the behavior of WATTACC[1:0] = 00.
11: absolute accumulation mode of the total and fundamental active powers. Fundamental active
powers are available in the ADE7878A only. This mode is observed only in the CFx output. The
accumulation in the registers continues to be a signed accumulation as in the case of WATTACC[1:0]
being set to 00.
[3:2] VARACC[1:0]
00
00: signed accumulation of the total and fundamental reactive powers. Total reactive powers are available
in the ADE7858A, ADE7868A, and ADE7878A. Fundamental reactive powers are available in the
ADE7878A only. These bits are always set to 00 for the ADE7854A.
01: reserved. When set, the device mimics the behavior of VARACC[1:0] = 00.
10: the total and fundamental reactive powers are accumulated, depending on the sign of the total and
fundamental active power. When the active power is positive, the reactive power accumulates as it is;
when the active power is negative, the reactive power accumulates with the reversed sign. This mode is
observed only in the CFx output. The accumulation in the registers continues to be a signed
accumulation as in the case of VARACC[1:0] being set to 00.
11: absolute accumulation mode of the total and fundamental reactive powers. Total reactive powers
are available in the ADE7858A, ADE7868A, and ADE7878A. Fundamental reactive powers are available
in the ADE7878A only. This mode is observed only in the CFx output. The accumulation in the registers
continues to be a signed accumulation as in the case of VARACC[1:0] being set to 00.
[5:4] CONSEL[1:0]
00
These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’are IA, IB, and IC shifted,
respectively, by −90°. See Table 50.
00: 3-phase, 4-wire wye with three voltage sensors.
01: 3-phase, 3-wire delta connection.
10: 3-phase, 4-wire wye with two voltage sensors.
11: 3-phase, 4-wire delta connection.
6
7
REVAPSEL
REVRPSEL
0
0
0: the total active power on each phase is used to trigger a bit in the STATUS0 register as follows: on
Phase A, triggers Bit 6 (REVAPA); on Phase B, triggers Bit 7 (REVAPB); and on Phase C, triggers Bit 8
(REVAPC). This bit is always set to 0 for the ADE7854A, ADE7858A, and ADE7868A.
1: the fundamental active power on each phase is used to trigger a bit in the STATUS0 register as
follows: on Phase A, triggers Bit 6 (REVAPA); on Phase B, triggers Bit 7 (REVAPB); and on Phase C, triggers
Bit 8 (REVAPC).
0: the total reactive power on each phase is used to trigger a bit in the STATUS0 register as follows: on
Phase A, triggers Bit 10 (REVRPA); on Phase B, triggers Bit 11 (REVRPB); and on Phase C, triggers Bit 12
(REVRPC). This bit is always set to 0 for the ADE7854A, ADE7858A, and ADE7868A.
1: the fundamental reactive power on each phase is used to trigger a bit in the STATUS0 register as
follows: on Phase A triggers Bit 10 (REVRPA), on Phase B triggers Bit 11 (REVRPB), and on Phase C
triggers Bit 12 (REVRPC).
Rev. D | Page 93 of 96
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