Data Sheet
ADE7854A/ADE7858A/ADE7868A/ADE7878A
Bits
Bit Name
Default Value
Description
10
CF2DIS
1
Setting this bit to 1 disables the CF2 output. The respective digital to frequency converter
remains enabled even when CF2DIS = 1.
Setting this bit to 0 enables the CF2 output.
11
CF3DIS
1
Setting this bit to 1 disables the CF3 output. The respective digital to frequency converter
remains enabled even when CF3DIS = 1.
Setting this bit to 0 enables the CF3 output.
12
13
14
15
CF1LATCH
CF2LATCH
CF3LATCH
Reserved
0
0
0
0
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF1 pulse is generated. See the Synchronizing Energy Registers with the CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF2 pulse is generated. See the Synchronizing Energy Registers with the CFx Outputs section.
When this bit is set to 1, the content of the corresponding energy registers is latched when a
CF3 pulse is generated. See the Synchronizing Energy Registers with the CFx Outputs section.
Reserved. This bit does not manage any functionality.
Table 44. APHCAL, BPHCAL, CPHCAL Registers (Address 0xE614, Address 0xE615, Address 0xE616)
Bits
Bit Name
Default Value
Description
[9:0]
PHCALVAL
0000000000
When the current leads the voltage, these bits can vary between 0 and 383 only.
When the current lags the voltage, these bits can vary between 512 and 575 only.
When the PHCALVAL bits are set with numbers between 384 and 511, the compensation
behaves similar to PHCALVAL set between 256 and 383.
When the PHCALVAL bits are set with numbers between 576 and 1023, the compensation
behaves similar to PHCALVAL bits set between 384 and 511.
[15:10]
Reserved
000000
Reserved. These bits do not manage any functionality.
Table 45. PHSIGN Register (Address 0xE617)
Bits
Bit Name
Default Value
Description
0
AWSIGN
0
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
1
2
3
4
5
6
BWSIGN
0
0
0
0
0
0
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
CWSIGN
0: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive.
1: if the active power identified by Bit 6 (REVAPSEL) in the ACCMODE register (total of
fundamental) on Phase C is negative.
SUM1SIGN
AVARSIGN
BVARSIGN
CVARSIGN
0: if the sum of all phase powers in the CF1 datapath is positive.
1: if the sum of all phase powers in the CF1 datapath is negative. Phase powers in the CF1
datapath are identified by Bits[2:0] (TERMSEL1[x]) of the COMPMODE register and by
Bits[2:0] (CF1SEL[x]) of the CFMODE register.
0: when the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is positive. This bit is always set to 0 for the ADE7854A.
1: when the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase A is negative.
0: when the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase B is positive. This bit is always set to 0 for the ADE7854A.
1: when the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase B is negative.
0: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase C is positive. This bit is always set to 0 for the ADE7854A.
1: if the reactive power identified by Bit 7 (REVRPSEL) in the ACCMODE register (total of
fundamental) on Phase C is negative.
Rev. D | Page 91 of 96
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