ADCMP580

更新时间： 2024-01-22 05:52:22

品牌	Logo	应用领域
亚德诺 - ADI		比较器
页数	文件大小	规格书
16页	416K
描述
Ultrafast SiGe Voltage Comparators

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技术参数
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ADCMP580 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	16
Reach Compliance Code：	unknown	风险等级：	5.39
放大器类型：	COMPARATOR	最大平均偏置电流 (IIB)：	30 µA
最大输入失调电压：	10000 µV	JESD-30 代码：	S-XQCC-N16
JESD-609代码：	e3	长度：	3 mm
湿度敏感等级：	3	负供电电压上限：	-6 V
标称负供电电压 (Vsup)：	-5 V	功能数量：	1
端子数量：	16	最高工作温度：	125 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	COMMERCIAL	标称响应时间：	0.18 ns
座面最大高度：	0.9 mm	子类别：	Comparator
供电电压上限：	6 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	AUTOMOTIVE	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	3 mm	Base Number Matches：	1

ADCMP580 数据手册

ADCMP580/ADCMP581/ADCMP582

APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

GND

The ADCMP58x family of comparators is designed for very

high speed applications. Consequently, high speed design

techniques must be used to achieve the specified performance.

It is critically important to use low impedance supply planes,

particularly for the negative supply (ꢀ_EE), the output supply

plane (ꢀ_CCO), and the ground plane (GND). Individual supply

planes are recommended as part of a multilayer board. Provid-

ing the lowest inductance return path for the switching currents

ensures the best possible performance in the target application.

50Ω

16mA

It is also important to adequately bypass the input and output

supplies. A 1 μF electrolytic bypass capacitor should be placed

within several inches of each power supply pin to ground. In

addition, multiple high quality 0.1 μF bypass capacitors should

be placed as close as possible to each of the ꢀ_EE, ꢀ_CCI, and ꢀ_CCO

supply pins and should be connected to the GND plane with

redundant vias. High frequency bypass capacitors should be

carefully selected for minimum inductance and ESR. Parasitic

layout inductance should be strictly avoided to maximize the

effectiveness of the bypass at high frequencies.

Figure 24. Simplified Schematic Diagram

of the ADCMP580 CML Output Stage

GND / Vcco

ADCMP58x FAMILY OF OUTPUT STAGES

Specified propagation delay dispersion performance is achieved

by using proper transmission line terminations. The outputs of

the ADCMP580 family comparators are designed to directly

drive 400 mꢀ into 50 Ω cable or microstrip/stripline transmis-

sion lines terminated with 50 Ω referenced to the proper return.

The CML output stage is shown in the simplified schematic

diagram in Figure 24. Each output is back-terminated with

50 Ω for best transmission line matching. The outputs of the

ADCMP581/ADCMP582 are illustrated in Figure 25; they

should be terminated to −2 ꢀ for ECL outputs of ADCMP581

and ꢀ_CCO− 2 ꢀ for PECL outputs of ADCMP582. As an alter-

native, Thevenin equivalent termination networks may also be

used. If these high speed signals must be routed more than a

centimeter, then either microstrip or stripline techniques are

required to ensure proper transition times and to prevent

excessive output ringing and pulse width-dependent

Figure 25. Simplified Schematic Diagram of the

ADCMP581/ADCMP582 ECL/PECL Output Stage

USING/DISABLING THE LATCH FEATURE

The latch inputs (LE/ ) are active low for latch mode and are

internally terminated with 50 Ω resistors to the ꢀ_TTpin. When

using the ADCMP580, ꢀ_TTshould be connected to ground.

When using the ADCMP581, ꢀ_TTshould be connected to

−2 ꢀ. When using the ADCMP582, ꢀ_TTshould be connected

externally to ꢀ_CCO− 2 ꢀ, preferably with its own low inductance

plane.

propagation delay dispersion.

When using the ADCMP580/ADCMP582, the latch function

can be disabled by connecting the

pin to ꢀ_EEwith an

external pull-down resistor and leaving the LE pin discon-

nected. To prevent excessive power dissipation, the resistor

should be 1.5 kΩ for the ADCMP580 and 1 kΩ for the

ADCMP582. When using the ADCMP581 comparators, the

latch can be disabled by connecting the LE pin to GND with

an external 450 Ω resistor and leaving the

pin disconnected.

The idea is to create an approximate 0.5 ꢀ offset using the

internal resistor as half of the voltage divider. The ꢀ_TTpin

should be connected as recommended.

Rev. 0 | Page 11 of 16

1...8 9 101112 13 14...16

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ADCMP580_15	ADI	Ultrafast SiGe Voltage Comparators	获取价格
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