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ADC32J24

更新时间： 2024-02-14 14:36:33
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
85页 3797K
描述
ADC32J2x Dual-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with JESD204B Interface

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ADC32J24 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFN
包装说明：VQFN-48针数：48
Reach Compliance Code：compliantECCN代码：3A991C2
Factory Lead Time：6 weeks风险等级：1.73
Is Samacsys：N最大模拟输入电压：2 V
最小模拟输入电压：-2 V转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：S-PQCC-N48JESD-609代码：e4
长度：7 mm湿度敏感等级：3
模拟输入通道数量：2位数：12
功能数量：1端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY输出格式：SERIAL
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260采样速率：160 MHz
座面最大高度：1 mm标称供电电压：1.8 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7 mm
Base Number Matches：1

ADC32J24 数据手册

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ADC32J22, ADC32J23, ADC32J24, ADC32J25  
SBAS668A –MAY 2014–REVISED JUNE 2015  
ADC32J2x Dual-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter  
with JESD204B Interface  
1 Features  
3 Description  
The ADC32J2x is a high-linearity, ultra-low power,  
dual-channel, 12-bit, 50-MSPS to 160-MSPS, analog-  
to-digital converter (ADC) family. The devices are  
designed specifically to support demanding, high  
input frequency signals with large dynamic range  
requirements. A clock input divider allows more  
flexibility for system clock architecture design and the  
1
•
Dual Channel  
•
•
•
•
12-Bit Resolution  
Single 1.8-V Supply  
Flexible Input Clock Buffer with Divide-by-1, -2, -4  
SNR = 70.3 dBFS, SFDR = 88 dBc at  
fIN = 70 MHz  
SYSREF  
input  
enables  
complete  
system  
•
Ultralow Power Consumption:  
synchronization. The devices support JESD204B  
interfaces in order to reduce the number of interface  
lines, thus allowing for high system integration  
density. The JESD204B interface is a serial interface,  
where the data of each ADC are serialized and output  
over only one differential pair. An internal phase-  
locked loop (PLL) multiplies the incoming ADC  
sampling clock by 20 to derive the bit clock that is  
used to serialize the 12-bit data from each channel.  
The devices support subclass 1 with interface speeds  
up to 3.2 Gbps.  
–
227 mW/Ch at 160 MSPS  
•
•
•
Channel Isolation: 105 dB  
Internal Dither  
JESD204B Serial Interface:  
–
–
Subclass 0, 1, 2 Compliant up to 3.2 Gbps  
Supports One Lane per ADC up to 160 MSPS  
•
•
Support for Multichip Synchronization  
Pin-to-Pin Compatible with 14-Bit Version  
(ADC32J4X)  
Device Information(1)  
•
Package: VQFN-48 (7 mm × 7 mm)  
PART NUMBER  
PACKAGE  
BODY SIZE (NOM)  
ADC32J2X  
VQFN (48)  
7.00 mm × 7.00 mm  
2 Applications  
(1) For all available packages, see the package option addendum  
at the end of the datasheet.  
•
•
•
•
•
•
•
•
•
•
Multi-Carrier, Multi-Mode Cellular Base Stations  
Radar and Smart Antenna Arrays  
Munitions Guidance  
FFT with Dither On  
(fS = 160 MSPS, SNR = 70.3 dBFS, fIN = 10 MHz,  
SFDR = 92.6 dBc)  
Motor Control Feedback  
Network and Vector Analyzers  
Communications Test Equipment  
Nondestructive Testing  
0
-10  
-20  
Microwave Receivers  
-30  
Software Defined Radios (SDRs)  
Quadrature and Diversity Radio Receivers  
-40  
-50  
-60  
-70  
-80  
-90  
-100  
-110  
-120  
0
16  
32  
48  
64  
80  
Frequency (MHz)  
D201  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
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