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ADC12C170CISQ PDF预览

ADC12C170CISQ

更新时间： 2024-11-25 04:48:51
品牌 Logo 应用领域
美国国家半导体 - NSC 转换器模数转换器
页数 文件大小 规格书
22页 425K
描述
12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with CMOS outputs

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ADC12C170CISQ 技术参数

是否Rohs认证：不符合生命周期：Transferred
包装说明：7 X 7 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, LLP-48Reach Compliance Code：not_compliant
ECCN代码：3A991.C.2HTS代码：8542.39.00.01
风险等级：5.43Is Samacsys：N
最大模拟输入电压：1.6 V最小模拟输入电压：1.4 V
最长转换时间：0.041 µs转换器类型：ADC, PROPRIETARY METHOD
JESD-30 代码：S-XQCC-N48JESD-609代码：e0
长度：7 mm最大线性误差 (EL)：0.072%
湿度敏感等级：3模拟输入通道数量：1
位数：12功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出位码：OFFSET BINARY, 2'S COMPLEMENT BINARY
输出格式：PARALLEL, WORD封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC48,.27SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified采样速率：170 MHz
采样并保持/跟踪并保持：SAMPLE座面最大高度：0.8 mm
子类别：Analog to Digital Converters标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：7 mmBase Number Matches：1

ADC12C170CISQ 数据手册

 浏览型号ADC12C170CISQ的Datasheet PDF文件第2页浏览型号ADC12C170CISQ的Datasheet PDF文件第3页浏览型号ADC12C170CISQ的Datasheet PDF文件第4页浏览型号ADC12C170CISQ的Datasheet PDF文件第5页浏览型号ADC12C170CISQ的Datasheet PDF文件第6页浏览型号ADC12C170CISQ的Datasheet PDF文件第7页 
February 2007  
ADC12C170  
12-Bit, 170 MSPS, 1.1 GHz Bandwidth A/D Converter with  
CMOS outputs  
General Description  
Features  
The ADC12C170 is a high-performance CMOS analog-to-  
digital converter capable of converting analog input signals  
into 12-Bit digital words at rates up to 170 Mega Samples Per  
Second (MSPS). This converter uses a differential, pipelined  
architecture with digital error correction and an on-chip sam-  
ple-and-hold circuit to minimize power consumption and the  
external component count, while providing excellent dynamic  
performance. A unique sample-and-hold stage yields a full-  
power bandwidth of 1.1 GHz. The ADC12C170 operates from  
dual +3.3V and +1.8V power supplies and consumes 715 mW  
of power at 170 MSPS.  
1.1 GHz Full Power Bandwidth  
■
■
■
■
■
■
■
■
Internal sample-and-hold circuit  
Low power consumption  
Internal precision 1.0V reference  
Single-ended or Differential clock modes  
Clock Duty Cycle Stabilizer  
Dual +3.3V and +1.8V supply operation (+/- 10%)  
Power-down and Sleep modes  
Offset binary or 2's complement output data format  
■
■
■
Pin-compatible with: ADC14155  
The separate +1.8V supply for the digital output interface al-  
lows lower power operation with reduced noise. A power-  
down feature reduces the power consumption to 5 mW while  
still allowing fast wake-up time to full operation. In addition  
there is a sleep feature which consumes 50 mW of power and  
has a faster wake-up time.  
48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)  
Key Specifications  
Resolution  
Conversion Rate  
12 Bits  
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■
■
■
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170 MSPS  
67.2 dBFS (typ)  
85.4 dBFS (typ)  
10.8 bits (typ)  
1.1 GHz (typ)  
715 mW (typ)  
The differential inputs provide a full scale differential input  
swing equal to 2 times the reference voltage. A stable 1.0V  
internal voltage reference is provided, or the ADC12C170 can  
be operated with an external reference.  
SNR (fIN = 70 MHz)  
SFDR (fIN = 70 MHz)  
ENOB (fIN = 70 MHz)  
Full Power Bandwidth  
Power Consumption  
Clock mode (differential versus single-ended) and output data  
format (offset binary versus 2's complement) are pin-se-  
lectable. A duty cycle stabilizer maintains performance over  
a wide range of input clock duty cycles.  
Applications  
The ADC12C170 is pin compatible with the ADC14155.  
High IF Sampling Receivers  
■
■
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It is available in a 48-lead LLP package and operates over the  
industrial temperature range of −40°C to +85°C.  
Wireless Base Station Receivers  
Power Amplifier Linearization  
Multi-carrier, Multi-mode Receivers  
Test and Measurement Equipment  
Communications Instrumentation  
Radar Systems  
Block Diagram  
20209202  
© 2007 National Semiconductor Corporation  
202092  
www.national.com  
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