Datasheet > ADC124S021CIMMX/NOPB

ADC124S021CIMMX/NOPB

更新时间： 2022-10-12 16:20:27

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
27页	1370K
描述
4-Channel, 50 ksps to 200 ksps, 12-Bit A/D Converter

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ADC104S101

SNAS284F –FEBRUARY 2005–REVISED MARCH 2013

www.ti.com

Block Diagram

IN1

10-Bit

SUCCESSIVE

APPROXIMATION

ADC

MUX

T/H

GND

IN4

SCLK

CONTROL

LOGIC

DIN

DOUT

Pin Descriptions and Equivalent Circuits

Pin No.

ANALOG I/O

4-7

Pin Name

Description

IN1 to IN4

Analog inputs. These signals can range from 0V to V_A.

DIGITAL I/O

SCLK

DOUT

Digital clock input. This clock directly controls the conversion and readout processes.

Digital data output. The output samples are clocked out of this pin on falling edges of the

SCLK pin.

Digital data input. The ADC104S101's Control Register is loaded through this pin on rising

edges of the SCLK pin.

DIN

Chip select. On the falling edge of CS, a conversion process begins. Conversions continue

as long as CS is held low.

POWER SUPPLY

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and

bypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1

cm of the power pin.

V_A

GND

The ground return for the supply and signals.

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