Datasheet > ADC124S021CIMMX/NOPB

ADC124S021CIMMX/NOPB

更新时间： 2022-10-12 16:20:27

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
27页	1370K
描述
4-Channel, 50 ksps to 200 ksps, 12-Bit A/D Converter

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ADC104S101

SNAS284F –FEBRUARY 2005–REVISED MARCH 2013

www.ti.com

ADC104S101 Timing Specifications

The following specifications apply for V_A= +2.7V to 5.25V, GND = 0V, C_L= 50 pF, f_SCLK= 8 MHz to 16 MHz, f_SAMPLE= 500

ksps to 1 Msps, Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25°C.

Parameter

Test Conditions

V_A= +3.0V

Typical

−3.5

−0.5

+4.5

+1.5

Limits⁽¹⁾

Units

t_CSU

t_CLH

t_EN

Setup Time SCLK High to CS Falling Edge

See⁽²⁾

ns (min)

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

Hold time SCLK Low to CS Falling Edge

Delay from CS Until DOUT active

ns (min)

ns (max)

+16.5

+15

t_ACC

Data Access Time after SCLK Falling Edge

t_SU

t_H

t_CH

t_CL

Data Setup Time Prior to SCLK Rising Edge

Data Valid SCLK Hold Time

SCLK High Pulse Width

ns (min)

0.5 x t_SCLK0.3 x t_SCLKns (min)

SCLK Low Pulse Width

0.5 x t_SCLK0.3 x t_SCLKns (min)

V_A= +3.0V

V_A= +5.0V

V_A= +3.0V

V_A= +5.0V

1.7

1.2

Output Falling

Output Rising

t_DIS

CS Rising Edge to DOUT High-Impedance

ns (max)

1.0

(1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).

(2) Clock may be either high or low when CS is asserted as long as setup and hold times t_CSUand t_CLHare strictly observed.

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