Datasheet > ADAU1962AWBSTZ

ADAU1962AWBSTZ

更新时间： 2022-02-26 12:30:13

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
48页	1331K
描述
12-Channel, High Performance, DAC

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ADAU1962AWBSTZ 数据手册

Data Sheet

ADAU1962A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

DAC_BIAS3

DAC_BIAS4

AVDD3

DAC_BIAS2

DAC_BIAS1

AVDD2

PIN 1

INDICATOR

DAC4N

DAC4P

DAC3N

DAC3P

DAC2N

DAC2P

ADAU1962A

DAC1N

TOP VIEW

DAC1P

(Not to Scale)

AVDD4

AGND4

PLLGND

AVDD1

AGND1

PU/RST

SA_MODE

SS/ADDR0/SA

SCLK/SCL

MISO/SDA/SA

MOSI/ADDR1/SA

DVDD

PLLVDD

MCLKI/XTALI

XTALO

MCLKO

DVDD

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. SEE THE STANDALONE MODE SECTION (TABLE 13 AND TABLE 14) FOR THE SA_MODE SETTINGS

FOR PIN 31, PIN 32, PIN 42, PIN 43, AND PIN 45.

Figure 3. Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic^{1, 2}

DAC_BIAS3

DAC_BIAS4

AVDD3

AVDD4

AGND4

PLLGND

PLLVDD

MCLKI/XTALI

XTALO

Type³Description

DAC Bias 3. AC couple with a 470 nF to AGND3.

DAC Bias 4. AC couple with a 470 nF to AVDD3.

Analog Power.

No Connect. Do not connect to these pins.

Analog Power.

Analog Ground.

PLL Ground.

PLL Loop Filter. Reference the LF pin to PLLVDD.

PLL Power. Apply 2.5 V to power the PLL.

Master Clock Input/Input to Crystal Inverter. This is a multifunction pin.

Output from Crystal Inverter.

Master Clock Output.

PWR

GND

PWR

4 to 11

20, 29, 41

21, 26, 30, 40 DGND

22, 39

MCLKO

DVDD

PWR

GND

PWR

Digital Power, 2.5 V.

Digital Ground.

IOVDD

VSENSE

Power for Digital Input and Output Pins, 3.3 V.

2.5 V Regulator Output, Pass Transistor Collector. Bypass VSENCE with a 10 μF capacitor in

parallel with a 100 nF capacitor.

VDRIVE

Pass Transistor Base Driver.

Rev. A | Page 9 of 48

1...6 7 8910 11 12...48

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