ADAU1962A
Data Sheet
DIGITAL FILTERS
Table 6.
Parameter
Mode
Factor
Min Typ Max
Unit
DAC INTERPOLATION FILTER
Pass Band
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
192 kHz low propagation delay mode, typical at 192 kHz
0.4535 × fS
0.3646 × fS
0.3646 × fS
22
70
kHz
kHz
kHz
35
Pass-Band Ripple
Transition Band
Stop Band
0.01 dB
0.05 dB
0.1
dB
0.5 × fS
0.5 × fS
0.5 × fS
0.5465 × fS
0.6354 × fS
0.6354 × fS
24
48
96
26
61
122
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
Stop-Band Attenuation
Propagation Delay
68
68
68
25/fS
11/fS
8/fS
521
115
42
μs
μs
2/fS
10
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 2.5 V 10ꢀ, unless otherwise noted.
Table 7.
Parameter
Description
Min Typ Max Unit
INPUT MASTER CLOCK (MCLKI) AND RESET
tMH
Master clock duty cycle, DAC clock source = PLL clock at
256 × fS, 384 × fS, 512 × fS, and 768 × fS
40
60
60
%
%
DAC clock source = direct MCLKI at 512 × fS (bypass on- 40
chip PLL)
fMCLK
MCLKI frequency of the MCLKI/XTALI pin, PLL mode
Direct MCLKI 512 × fS mode
DBCLK pin frequency, PLL mode
Low
6.9
40.5 MHz
27.1 MHz
27.0 MHz
ns
fBCLK
tPDR
15
tPDRR
Recovery, reset to active output
300
ms
PLL
Lock Time
MCLKI input of the MCLKI/XTALI pin
DLRCLK pin input
256 × fS VCO clock
10
50
60
ms
ms
%
Output Duty Cycle, MCLKO Pin
40
Rev. A | Page 6 of 48