Datasheet > 消费电路 > 音频/视频放大器> ADAU1590ACPZ-RL7

ADAU1590ACPZ-RL7

更新时间： 2024-01-12 07:01:16

品牌	Logo	应用领域
亚德诺 - ADI		消费电路商用集成电路音频放大器视频放大器功率放大器
页数	文件大小	规格书
24页	588K
描述
Class-D Audio Power Amplifier

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技术参数
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替代型号

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ADAU1590ACPZ-RL7 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN, LCC48,.27SQ,20	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.33.00.01	风险等级：	5.66
标称带宽：	20 kHz	商用集成电路类型：	AUDIO AMPLIFIER
JESD-30 代码：	S-XQCC-N48	JESD-609代码：	e3
长度：	7 mm	信道数量：	2
功能数量：	1	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
标称输出功率：	15.5 W	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC48,.27SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3,12 V
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	Audio/Video Amplifiers	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm	Base Number Matches：	1

ADAU1590ACPZ-RL7 数据手册

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ADAU1590

AVDD/DVDD

PVDD

POWER-UP/POWER-DOWN SEQUENCE

Figure 43 shows the recommended power-up sequence for the

ADAU1590.

AVDD/DVDD

STDN

t_INT

PVDD

INTERNAL MUTE

t_WAIT

MUTE

STDN

t_INT

PVDD/2

INTERNAL MUTE

OUTx+/OUTx–

AINx

t_PDL-H

AVDD/2

t_WAIT

MUTE

PVDD/2

t_INT= 650ms @ 24.576MHz CLOCK

t_WAIT< T

INT

OUTx+/OUTx–

NOTES

AVDD/2

1. INTERNAL MUTE IS INTERNAL TO CHIP.

AINx

Figure 44. Power-Up Sequence, t_WAIT< t_INT

t_INT= 650ms @ 24.576MHz CLOCK

t_PDL-H= 200µs

The ADAU1590 uses three separate supplies: AVDD (3.3 V

analog for PGA and modulator), DVDD (3.3 V digital for

control logic and clock oscillator), and PVDD (9 V to 18 V

power stage and level shifter). Separate pins are provided for

the AVDD, DVDD, and PVDD supply connections, as well as

AGND, DGND, and PGND.

t_WAIT= 10 × R × C

NOTES

1. INTERNAL MUTE IS INTERNAL TO CHIP.

Figure 43. Recommended Power-Up Sequence

The ADAU1590 has a special turn-on sequence that consists of

a fixed internal mute time during which the power stage does

not start switching. This internal mute time depends on the

master clock frequency and is 650 ms for a 24.576 MHz clock.

In addition, the ADAU1590 incorporates a built-in undervolt-

age lockout logic on DVDD as well as PVDD. This helps detect

undervoltage operation and eliminates the need to have an external

mechanism to sense the supplies.

MUTE

Also, the internal mute overrides the external

ensures that the power stage does not switch on immediately

MUTE

and

even if the external

signal is pulled high in less than

. The power stage starts switching only

after 650 ms plus a small propagation delay of 200 μs has

MUTE

The ADAU1590 monitors the DVDD and PVDD supply voltages

and prevents the power stage from turning on if either of the

supplies are not present or are below the operating threshold.

Therefore, if DVDD is missing or below the operating thresh-

old, for example, the power stage does not turn on, even if

PVDD is present, or vice versa.

STDN

650 ms after

elapsed and after

is deasserted. Therefore, it is recom-

mended to ensure that t_WAIT> t_INTto prevent the pop and click

during power-on.

MUTE

Ensure that the

signal is delayed by at least t_WAITseconds

Because this protection is only present on DVDD and PVDD

and not on AVDD, shorting both AVDD and DVDD externally

or generating AVDD and DVDD from one power source is

recommended. This ensures that both AVDD and DVDD

supplies are tracking each other and avoids the need to monitor

the sequence with respect to PVDD. This also ensures minimal

pop and click during power-up.

STDN

after

. This time is approximately 10 times the charging

time constant of the input coupling capacitor.

For example, if the input coupling capacitor is 4.7 μF, the time

constant is

T = R × C = 20 kꢀ × 4.7 μF = 94 ms

Therefore, t_WAIT= 10 × T = 940 ms ~ 1 sec.

When using separate AVDD and DVDD supplies, ensure that

both supplies are stable before unmuting or turning on the

power stage.

_WAITis needed to ensure that the input capacitors are charged to

AVDD/2 before turning on the power stage.

MUTE

Similarly, during shutdown, pulling

to logic low before

When t_WAIT< t_INT, the power stage does not start switching until

STDN

650 ms has elapsed after

that this method does not ensure pop-and-click suppression

because of less than recommended or insufficient t_WAIT

(see Figure 44). However, note

pulling

down is recommended. However, where a fault

event occurs, the power stage shuts down to protect the part. In

this case, depending on the signal level, there is some pop at the

speaker.

Rev. 0 | Page 18 of 24

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ADAU1590ACPZ-RL7 替代型号

型号	品牌	替代类型	描述	数据表
AD1990ACPZRL7	ADI	类似代替	Audio Switching Amplifier
AD1990ACPZRL	ADI	类似代替	Audio Switching Amplifier

与ADAU1590ACPZ-RL7相关器件

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ADAU1590ASVZRL7	ADI	获取价格	Class-D Audio Power Amplifier
ADAU1592	ADI	获取价格	Class-D Audio Power Amplifier
ADAU1592ACPZ	ADI	获取价格	Class-D Audio Power Amplifier
ADAU1592ACPZ-RL	ADI	获取价格	Class-D Audio Power Amplifier
ADAU1592ACPZ-RL7	ADI	获取价格	Class-D Audio Power Amplifier
ADAU1592ASVZ	ADI	获取价格	Class-D Audio Power Amplifier
ADAU1592ASVZ-RL	ADI	获取价格	Class-D Audio Power Amplifier
ADAU1592ASVZ-RL7	ADI	获取价格	Class-D Audio Power Amplifier

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