ADAU1781

更新时间： 2024-01-19 13:56:13

品牌	Logo	应用领域
亚德诺 - ADI		解码器编解码器
页数	文件大小	规格书
88页	908K
描述
Low Noise Stereo Codec with SigmaDSP Processing Core

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技术参数
数据手册

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ADAU1781 技术参数

生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	32
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.68	Is Samacsys：	N
商用集成电路类型：	CONSUMER CIRCUIT	JESD-30 代码：	S-XQCC-N32
长度：	5 mm	功能数量：	1
端子数量：	32	最高工作温度：	85 °C
最低工作温度：	-25 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	认证状态：	Not Qualified
座面最大高度：	1 mm	最大供电电压 (Vsup)：	3.65 V
最小供电电压 (Vsup)：	1.8 V	表面贴装：	YES
温度等级：	OTHER	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	5 mm	Base Number Matches：	1

ADAU1781 数据手册

Low Noise Stereo Codec with

SigmaDSP Processing Core

ADAU1781

FEATURES

GENERAL DESCRIPTION

24-bit stereo audio ADC and DAC

400 mW speaker amplifier (into 8 Ω load)

Programmable SigmaDSP audio processing core

Wind noise detection and filtering

Enhanced stereo capture (ESC)

The ADAU1781 is a low power, 24-bit stereo audio codec. The

low noise DAC and ADC support sample rates from 8 kHz to

96 kHz. Low current draw and power saving modes make the

ADAU1781 ideal for battery-powered audio applications.

A programmable SigmaDSP® core provides enhanced record

and playback processing to improve overall audio quality.

Dynamics processing

Equalization and filtering

Volume control and mute

The record path includes two digital stereo microphone inputs

and an analog stereo input path. The analog inputs can be

configured for either a pseudo differential or a single-ended

stereo source. A dedicated analog beep input signal can be

mixed into any output path. The ADAU1781 includes a stereo

line output and speaker driver, which makes the device capable of

supporting dynamic speakers.

Sampling rates from 8 kHz to 96 kHz

Stereo pseudo differential microphone input

Optional stereo digital microphone input pulse-density

modulation (PDM)

Stereo line output

PLL supporting a range of input clock rates

Analog and digital I/O 1.8 V to 3.3 V

Software control via SigmaStudio graphical user interface

Software-controllable, clickless mute

Software register and hardware pin standby mode

32-lead, 5 mm × 5 mm LFCSP

The serial control bus supports the I²C® or SPI protocols, and

the serial audio bus is programmable for I²S, left-justified, right-

justified, or TDM mode. A programmable PLL supports flexible

clock generation for all standard rates and available master clocks

from 11 MHz to 20 MHz.

APPLICATIONS

Digital still cameras

Digital video cameras

FUNCTIONAL BLOCK DIAGRAM

ADAU1781

REGULATOR

BEEP

PGA

SigmaDSP CORE

WIND NOISE

AOUTL

AOUTR

LMIC/LMICN/

MICD1

LEFT

ADC

LEFT

DAC

NOTCH FILTER

EQUALIZER

PGA

LMICP

OUTPUT

MIXER

DIGITAL VOLUME

CONTROL

RMIC/RMICN/

MICD2

SPP

SPN

DYNAMIC

PROCESSING

RIGHT

DAC

PGA

ADC

RMICP

PDN

SERIAL DATA

INPUT/OUTPUT PORTS

I C/SPI

CONTROL PORT

MICROPHONE

BIAS

MICBIAS

PLL

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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