Datasheet > ADAR2004ACCZ

ADAR2004ACCZ

更新时间： 2024-02-19 11:39:41

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
37页	758K
描述
10 GHz to 40 GHz, 4-Channel Rx Mixer with 4Ã LO Multiplier/Filter

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ADAR2004ACCZ 数据手册

10 GHz to 40 GHz, 4-Channel Rx Mixer with

4× LO Multiplier/Filter

Data Sheet

ADAR2004

FEATURES

GENERAL DESCRIPTION

Quad LNA, mixer, IF VGA

The ADAR2004 is a 4-channel receiver IC that is optimized for

4× LO multiplier with programmable harmonic filter

RF input frequency range: 10 GHz to 40 GHz

IF output frequency range: 0 MHz to 800 MHz

LO input frequency range: 2.4 GHz to 10.1 GHz

Gain range: 21 dB to 41 dB

Input P1dB: −20 dBm typical (at minimum gain)

Noise figure: 9 dB typical (at maximum gain)

3-wire or 4-wire SPI control

On-chip programmable state machines for fast

multiplier/filter and receiver switching and control

On-chip temperature sensor and ADC

DC power: 910 mW (2.5 V supply)

7 mm × 7 mm, 48-terminal LGA package

millimeter wave body scanning applications. Accepting differential

input signals from 10 GHz to 40 GHz, the ADAR2004 provides a

low intermediate frequency (IF) output up to 800 MHz. Each

receive channel also has independent gain control.

The mixer local oscillator (LO) path includes a 4× multiplier

requiring an applied LO frequency between 2.4 GHz and

10.1 GHz. The 4× multiplier block includes a programmable filter

that helps keep harmonics down before reaching the mixer.

Two programmable state machines are included to facilitate

simple configuration, control, and fast switching of the frequency

multiplier, filter, and receiver sections. These sequencers are

programmed through the serial peripheral interface (SPI) and

are then operated by pulsed inputs (reset and advance).

APPLICATIONS

Millimeter wave imaging

Security

Medical

Industrial

The ADAR2004 requires only a single 2.5 V supply with power

consumption of 910 mW with all channels turned on.

The ADAR2004 is available in a 7 × 7 mm, 48-terminal LGA

package and is specified from −40°C to +85°C.

Multichannel receivers

FUNCTIONAL BLOCK DIAGRAM

ADAR2004

RECEIVER SEQUENCER

RFIN1+

RFIN1–

IFOUT1+

IFOUT1–

LNA

VGA

RFIN2+

RFIN2–

IFOUT2+

IFOUT2–

RFIN3+

RFIN3–

IFOUT3+

IFOUT3–

RFIN4+

RFIN4–

IFOUT4+

IFOUT4–

MULTIPLIER/FILTER SEQUENCER

×4

LOIN

BUFFER

×4

SDIO

SCLK

SDO

SPI

CONTROL

ADC

TEMPERATURE

SENSOR

MULTIPLIER/FILTER

STATE MACHINE

(16 STATES)

RECEIVER

STATE MACHINE

(16 STATES)

MRST

MADV

RxRST

RxADV

Figure 1.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice.

No license is granted by implication or otherwise under any patent or patent rights of Analog

Devices. Trademarks and registeredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

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