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ADAS1000

更新时间: 2024-09-24 08:18:31
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描述
Low Power, 5-Electrode Electrocardiogram (ECG) Analog Front End

ADAS1000 数据手册

 浏览型号ADAS1000的Datasheet PDF文件第2页浏览型号ADAS1000的Datasheet PDF文件第3页 
Low Power, 5-Electrode  
Electrocardiogram (ECG) Analog Front End  
ADAS1000  
Preliminary Technical Data  
FEATURES  
APPLICATIONS  
Biopotential signals in; digitized signals out  
5 acquisition (ECG) channels + 1 driven lead  
ECG: Monitor & Diagnostic  
Bedside Patient Monitoring, Portable Telemetry, Holter,  
Parallel ICs for up to 10+ Electrode measurements  
AC and DC Leads Off Detection  
AED, Cardiac Defibrillators, Ambulatory Monitors, Pace  
Maker Programmer, Patient Transport, Stress testing,  
Internal Pace Detection Algorithm on 3 leads  
Support for users own pace  
GENERAL DESCRIPTION  
The ADAS1000 measures electro cardiac (ECG) signals,  
thoracic impedance, pacing artifacts, lead on/off status and  
outputs this information in the form of a data frame supplying  
either Lead/Vector or Electrode data at programmable data  
rates. Its low power and small size make it suitable for portable,  
battery powered applications. The high performance also makes  
it suitable for higher end diagnostic machines.  
Thoracic Impedance Measurement (internal/external path)  
Selectable Reference Lead  
Scalable Noise vs. Power Control  
Low Power Operation from:  
11mW (one lead), 14mW (3 leads), 19mW (all electrodes)  
Power Down Modes  
Lead or Electrode Data available  
Supports AAMI EC11:1991/(R)2001/(R)2007,  
EC13:2002/(R)2007, IEC60601-1 ed. 3.0b, 2005, IEC60601-  
2-25 ed. 1.0b, IEC60601-2-27 ed. 2.0, 2005 IEC60601-2-51  
ed. 1.0, 2005  
The ADAS1000 is designed to simplify the task of acquiring and  
ensuring quality ECG signals. Value-added cardiac post-  
processing is executed externally on a DSP, microprocessor or  
FPGA. Several digital output options ensure flexibility when  
monitoring and analyzing signals. The ADAS1000 provides a  
low power, small data acquisition system for biopotential  
applications.  
Fast Overload Recovery  
Low or High speed Data Output Rates  
Serial interface SPI®-/QSPI™-/DSP-compatible  
56 lead LFCSP package (8mm x8mm)  
64 lead LQFP package (10mm x10mm Body size)  
FUNCTIONAL BLOCK DIAGRAM  
CAL_DAC  
_IO  
SHIELD  
DRIVE  
REFIN REFOUT  
RLD_SJ  
RLD_FB RLD_OUT  
CM_IO  
DRIVEN  
LEAD  
Voltage  
Reference  
-
VCM  
(1.5V)  
AMP  
-
+
SHIELD  
DRIVE  
AMP  
CALIBRATION  
DAC  
+
RESPIRATION  
DAC  
AC LEADS  
OFF DAC  
COMMON  
MODE AMP  
LEADS  
OFF  
DETECTION  
PACE  
MUXES  
DETECTION  
CS  
SCLK  
STANDARD  
5 x ECG PATH  
SDI  
SERIAL INTERFACE  
FILTERS,  
ELECTRODES  
x 5  
SDO  
CONTROL  
&
INTERFACE  
LOGIC  
AMP  
ADC  
ADC  
DRDY  
SHIELD  
DRIVE  
GPIO0/MCS  
SECONDARY  
MASTER INTERFACE  
FOR PACE  
EXT RESP 1  
EXT RESP 2  
EXT RESP 3  
GPIO1/MSCLK  
AMP  
GPIO2/MSDO  
GPIO3  
OPTIONAL  
CLOCK GEN/OSC  
/EXTERNAL CLK  
SOURCE  
CLK_IO  
RESPIRATION PATH  
XTAL  
OUT  
XTAL  
IN  
8.192MHz  
Cyrstal or Clock  
Figure 1 Functional Block Diagram  
Rev. Pr.D  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed byAnalog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2011 Analog Devices, Inc. All rights reserved.  

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