AD9984
Preliminary Technical Data
Table 4.Pin Function Descriptions
Pin
Description
INPUTS
RAIN0
GAIN0
BAIN0
RAIN1
GAIN1
BAIN1
Analog Input for the Red Channel 0.
Analog Input for the Green Channel 0.
Analog Input for the Blue Channel 0.
Analog Input for the Red Channel 1.
Analog Input for the Green Channel 1.
Analog Input for the Blue Channel 1.
High impedance inputs that accept the red, green, and blue channel graphics signals, respectively. The three
channels are identical and can be used for any colors, but colors are assigned for convenient reference. They
accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to
support clamp operation.
HSYNC0
HSYNC1
Horizontal Sync Input Channel 0.
Horizontal Sync Input Channel 1.
These inputs receive a logic signal that establishes the horizontal timing reference and provides the frequency
reference for pixel clock generation. The logic sense of this pin can be automatically determined by the chip or
manually controlled by Serial Register 0x12, Bits [5:4] (Hsync polarity). Only the leading edge of Hsync is used by the
PLL; the trailing edge is used in clamp timing. When Hsync polarity = 0, the falling edge of Hsync is used. When Hsync
Polarity = 1 , the rising edge is active. The input includes a Schmitt trigger for noise immunity.
VSYNC0
VSYNC1
Vertical Sync Input Channel 0.
Vertical Sync Input Channel 1.
These are the inputs for vertical sync and provide timing information for generation of the field (odd/even) and
internal Coast generation. The logic sense of this pin can be automatically determined by the chip or manually
controlled by Serial Register 0x14, Bits [5:4] (Vsync polarity).
SOGIN0
SOGIN1
Sync-on-Green Input Channel 0.
Sync-on-Green Input Channel 1.
These inputs are provided to assist with processing signals with embedded sync, typically on the green channel. The
pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be
programmed in 8 mV steps to any voltage between 8 mV and 256 mV above the negative peak of the input signal.
The default voltage threshold is 128 mV. When connected to an AC coupled graphics signal with embedded sync, it
produces a noninverting digital output on SOGOUT. This is usually a composite sync signal, containing both vertical
and horizontal sync information that must be separated before passing the horizontal sync signal for Hsync
processing. When not used, this input should be left unconnected. For more details on this function and how it
should be configured, refer to the Sync-on-Green section.
CLAMP
External Clamp Input (Optional).
This logic input may be used to define the time during which the input signal is clamped to ground or midscale. It
should be exercised when the reference DC level is known to be present on the analog input channels, typically
during the back porch of the graphics signal. The CLAMP pin is enabled by setting the control bit clamp function to 1,
(Register 0x18, Bit 4; default is 0). When disabled, this pin is ignored and the clamp timing is determined internally by
counting a delay and duration from the trailing edge of the Hsync input. The logic sense of this pin can be auto-
matically determined by the chip or controlled by clamp polarity Register 0x1B, Bits [7:6]. When not used, this pin may
be left unconnected (there is an internal pull-down resistor) and the clamp function programmed to 0.
EXTCLK/COAST
Coast Input to Clock Generator (Optional).
This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a
clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce
Hsync pulses during the vertical interval. The coast signal is generally not required for PC-generated signals. The logic
sense of this pin can be determined automatically or controlled by Coast polarity (Register 0x18, Bits [7:6]). When not
used and EXTCLK not used, this pin may be grounded and Coast polarity programmed to 1. Input Coast polarity
defaults to1 at power-up. This pin is shared with the EXTCLK function, which does not affect coast functionality. For
more details on EXTCLK, see the description in this section.
EXTCLK/COAST
PWRDN
External Clock.
This allows the insertion of an external clock source rather than the internally generated, PLL locked clock. EXTCLK is
enabled by programming Register 0x03, Bit 2 to 1. This pin is shared with the Coast function, which does not affect
EXTCLK functionality. For more details on Coast, see the above description in this section.
Power-Down Control
This pin can be used along with Register 0x1E, Bit 3 for manual power-down control. If manual power-down control is
selected (Register 0x1E, Bit 4) and this pin is not used, it is recommended to set the pin polarity (Register 0x1E, Bit 2)
to active high and hardwire this pin to ground with a 10 kΩ resistor.
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