Datasheet > AD9984KSTZ-110

AD9984KSTZ-110

更新时间： 2024-02-26 22:29:04

品牌	Logo	应用领域
罗彻斯特 - ROCHESTER		接口集成电路
页数	文件大小	规格书
46页	1075K
描述
SPECIALTY INTERFACE CIRCUIT, PQFP80, LEAD FREE,PLASTIC,MS-026BEC,LQFP-80

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD9984KSTZ-110 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	80
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.58
接口集成电路类型：	INTERFACE CIRCUIT	JESD-30 代码：	S-PQFP-G80
JESD-609代码：	e3	长度：	14 mm
湿度敏感等级：	3	功能数量：	1
端子数量：	80	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压：	1.9 V	最小供电电压：	1.7 V
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

AD9984KSTZ-110 数据手册

Preliminary Technical Data

AD9984

REFLO

REFHI

Description

Input Amplifier Reference.

REFLO and REFHI are connected together through a 10 μF capacitor; These are used for stability in the input ADC

circuitry. See Figure 5.

FILT

External Filter Connection.

For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to

this pin. For optimal performance, minimize noise and parasitics on this node. For more information, see the PCB

Layout Recommendations section.

OUTPUTS

HSOUT

Horizontal Sync Output.

A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be

programmed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to

Hsync can always be determined.

VSOUT/A0

Vertical Sync Output.

Pin shared with A0, serial port address. This can be either a separated Vsync from a composite signal or a direct pass

through of the Vsync signal. The polarity of this output can be controlled via a serial bus bit. The placement and

duration in all modes can be set by the graphics transmitter or the duration can be set by Register 0x14 and Register

0x15. This pin is shared with the A0 function, which does not affect Vsync Output functionality. For more details on

A0, see the description in the Serial Control Port section.

SOGOUT

Sync-On-Green Slicer Output.

This pin outputs one of four possible signals (controlled by Register 0x1D, bits [1:0]): raw SOG, raw Hsync, regenerated

Hsync from the filter, or the filtered Hsync. See the sync processing block diagram (see Figure 8) to view how this pin

is connected. Other than slicing off SOG, the output from this pin gets no other additional processing on the AD9984.

Vsync separation is performed via the sync separator.

O/E FIELD

Odd/Even Field Bit for Interlaced Video. This output will identify whether the current field (in an interlaced signal) is

odd or even.

SERIAL PORT

SDA

Serial Port Data I/O.

SCL

Serial Port Data Clock.

VSOUT/A0

Serial Port Address Input 0.

Pin shared with VSOUT. This pin selects the LSB of the serial port device address, allowing two Analog Devices parts to

be on the same serial bus. A high impedance external pull-up resistor enables this pin to be read at power-up as 1, or

a high impedance, external pull-down resistor enables this pin to be read at power-up as a 0 and not interfere with

the VSOUT functionality. For more details on VSOUT, see the Outputs section in this table.

DATA OUTPUTS

RED [9:0]

GREEN [9:0]

BLUE [9:0]

Data Output, Red Channel.

Data Output, Green Channel.

Data Output, Blue Channel.

The main data outputs.

Bit 9 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling time is changed by

adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so

the timing relationship among the signals is maintained.

DATA CLOCK

OUTPUT

DATACK

Data Clock Output.

This is the main clock output signal used to strobe the output data and HSOUT into external logic. Four possible

output clocks can be selected with Register 0x20, Bits [7:6]. Three of these are related to the pixel clock (pixel clock,

90° phase-shifted pixel clock and 2× frequency pixel clock). They are produced either by the internal PLL clock

generator or EXTCLK and are synchronous with the pixel sampling clock. The fourth option for the data clock output

is an internally generated 1/2x pixel clock.

The sampling time of the internal pixel clock can be changed by adjusting the phase register (Register 0x04). When

this is changed, the pixel related DATACK timing is also shifted. The data, DATACK, and HSOUT outputs are all moved

so that the timing relationship among the signals is maintained.

Rev. PrB | Page 9 of 45

1...7 8 91011 12 13...46

下载PDF

与AD9984KSTZ-110相关器件

型号	品牌	描述	获取价格	数据表
AD9984KSTZ-140	ADI	IC SPECIALTY INTERFACE CIRCUIT, PQFP80, LEAD FREE,PLASTIC,MS-026BEC,LQFP-80, Interface IC:	获取价格
AD9984KSTZ-140	ROCHESTER	SPECIALTY INTERFACE CIRCUIT, PQFP80, LEAD FREE,PLASTIC,MS-026BEC,LQFP-80	获取价格
AD9984KSTZ-170	ROCHESTER	SPECIALTY INTERFACE CIRCUIT, PQFP80, LEAD FREE,PLASTIC,MS-026BEC,LQFP-80	获取价格
AD9984KSTZ-170	ADI	IC SPECIALTY INTERFACE CIRCUIT, PQFP80, LEAD FREE,PLASTIC,MS-026BEC,LQFP-80, Interface IC:	获取价格
AD9985	ADI	110 MSPS/140 MSPS Analog Interface for Flat Panel Displays	获取价格
AD9985/PCB	ADI	110 MSPS/140 MSPS Analog Interface for Flat Panel Displays	获取价格

与AD9984KSTZ-110相关文章

资料手册解读：UC3842参数和管脚说明
2024-05-22

3
一文带你了解无源晶振的负载电容为何要加两颗谐振电容CL1和CL2
2024-05-22

4
玻璃管保险丝与陶瓷管保险丝：区别与替代性探讨
2024-05-22

3
PCF8574资料解读：主要参数分析、引脚说明
2024-05-21

16

产品中心

服务支持

精选活动

关于我们

帮助中心

AD9984KSTZ-110

AD9984KSTZ-110 技术参数

AD9984KSTZ-110 数据手册

与AD9984KSTZ-110相关器件

与AD9984KSTZ-110相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD9984KSTZ-110

AD9984KSTZ-110 技术参数

AD9984KSTZ-110 数据手册

与AD9984KSTZ-110相关器件

与AD9984KSTZ-110相关文章

您还可以找

您在本页遇到什么问题？