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AD9984A

更新时间: 2022-04-23 23:00:11
品牌 Logo 应用领域
亚德诺 - ADI 显示器
页数 文件大小 规格书
44页 616K
描述
High Performance 10-Bit Display Interface

AD9984A 数据手册

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AD9984A  
0x25—Bit[6] HSYNC1 Polarity  
HSYNC COUNT  
This bit indicates the polarity of HSYNC1 input.  
0x26—Bits[7:0] Hsyncs per Vsync MSBs  
This register contains the 8 MSBs of the 12-bit counter that  
reports the number of Hsyncs per Vsync on the active input. It  
is useful for determining the mode and is an aid in setting the  
PLL divide ratio.  
Table 71. HSYNC1 Polarity Bit  
Value  
Result  
0
1
HSYNC1 polarity is negative.  
HSYNC1 polarity is positive.  
0x27—Bits[7:4] Hsyncs per Vsync LSBs  
0x25—Bit[5] VSYNC0 Polarity  
This register contains the four LSBs of the 12-bit counter that  
reports the number of Hsyncs per Vsync on the active input.  
This bit indicates the polarity of VSYNC0 input.  
Table 72. VSYNC0 Polarity Bit  
TEST REGISTERS  
0x28—Bits[7:0] Test Register 1  
Value  
Result  
0
1
VSYNC0 polarity is negative.  
VSYNC0 polarity is positive.  
Must be written to 0xBF for proper operation.  
0x29—Bits[7:0] Test Register 2  
Must be written to 0x02 for proper operation.  
0x2A—Bits[7:0] Test Register 3  
Read only bits for future use.  
0x25—Bit[4] VSYNC1 Polarity  
This bit indicates the polarity of VSYNC1 input.  
Table 73. VSYNC1 Polarity Bit  
Value  
Result  
0x2B—Bits[7:0] Test Register 4  
Read only bits for future use.  
0
1
VSYNC1 polarity is negative.  
VSYNC1 polarity is positive.  
0x25—Bit[3] COAST Polarity  
0x2C—Bits[7:5] Offset Hold  
This bit indicates the polarity of the external COAST signal.  
Must be written to default 0x00 for proper operation.  
0x2C—Bit[4] Auto-Offset Hold  
Table 74. COAST Polarity Bit  
Value  
Result  
This bit controls whether the auto-offset function runs  
0
1
COAST polarity is negative.  
COAST polarity is positive.  
continuously or only once and holds the result. Continuous  
updates are recommended because they allow the AD9984A to  
compensate for drift over time, temperature, and so on. If one-  
time updates are preferred, they should be performed every  
time the part is powered up and when there is a mode change.  
To perform a one-time update, auto-offset must first be enabled  
(Register 0x1B, Bit 5). Next, this bit (auto-offset hold) must first  
be set to 0 to let the auto-offset function operate and settle to a  
final value. Auto-offset hold should then be set to 1 to hold the  
offset values that the auto circuitry calculates. The AD9984A  
auto-offset circuits maximum settle time is 10 updates. For  
example, if the update frequency is set to once every 192 Hsyncs,  
the maximum settling time is 1920 Hsyncs (10 × 192 Hsyncs).  
0x25—Bit[2] CLAMP Polarity  
This bit indicates the polarity of the CLAMP signal.  
Table 75. CLAMP Polarity Bit  
Value  
Result  
0
1
CLAMP polarity is negative.  
CLAMP polarity is positive.  
0x25—Bit[1] Extraneous Pulse Detection  
A second output from the Hsync filter, this status bit tells  
whether extraneous pulses are present on the incoming sync  
signal. Often, extraneous pulses are used for copy protection, so  
this status bit can be used for this purpose.  
Table 77. Auto-Offset Hold Bit  
Value  
Result  
Table 76. Extraneous Pulse Detection Bit  
Value  
0
1
Allows auto-offset to continuously update.  
Disables auto-offset updates and holds the current  
auto-offset values.  
Result  
0
1
No extraneous pulses detected during active Hsync.  
Extraneous pulses detected during active Hsync.  
0x2C—Bits[3:0]  
0x25—Bit[0] Sync Filter Lock  
Must be written to 0x0 for proper operation.  
0x2D—Bits[7:0] Test Register 5  
When this bit is set to 1, the sync filter is locked. When set to 0,  
the sync filer is unlocked.  
Read/write bits for future use. Must be written to 0xE8 for  
proper operation.  
Rev. 0 | Page 38 of 44  
 
 

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