Preliminary Technical Data
AD9983A
0x2C—Bits[7:5] Auto-Offset Hold
Must be written to 0x00 for proper operation.
0x2C—Bit[4] Auto-Offset Hold
0x36—Bit[0] VCO Gear Select
This bit allows the VCO to select a lower ‘gear’ which enables it
to run lower pixel clocks while remaining in a more linear range.
A bit for controlling whether the auto-offset function runs
continuously or runs once and holds the result. Continuous
updates are recommended because this allows the AD9983A to
compensate for drift over time and temperature. If one-time
updates are preferred, these should be performed every time the
part is powered up and when there is a mode change. To do a
one-time update, first auto-offset must be enabled (Register
0x1B, Bit 5). Next, this bit (auto-offset hold) must first be set to
1 to let the auto-offset function operate and settle to a final
value. Auto-offset hold should then be set to 0 to hold the offset
values that the auto circuitry calculates. The AD9983A auto-
offset circuit’s maximum settle time is 10 updates. For example,
if the update frequency is set to once every 64 Hsyncs, then the
maximum settling time would be 640 Hsyncs (10 × 64 Hsyncs).
Table 79. VCO Gear Select
Select
Result
0
1
Normal VCO setting
Enables lower VCO clock output
0x3C—Bits[7:4] Test Bits
Must be set to 0x0 for proper operation.
0x3C—Bit[3] Auto Gain Matching Hold
A bit for controlling whether the auto gain matching function
runs continuously or runs once and holds the result.
Continuous updates are recommended because it allows the
AD9983A to compensate for drift over time and temperature.
If one-time updates are preferred, these should be performed
every time the part is powered up and when there is a mode
change. To do a one-time update, first auto gain matching must
be enabled (Register Ox3C, Bit 2). Next, this bit (Auto Gain
Matching Hold) must first be set to 1 to let the auto gain
matching function operate and settle to a final value. The Auto
Gain Matching Hold bit should then be set to 0 to hold the gain
values that the auto circuitry calculates. The AD9983A auto gain
matching circuit’s maximum settle time is 10 updates. For example,
if the update frequency is set to once every 64 Hsyncs, then the
maximum settling time would be 640 Hsyncs (10 x 64 Hsyncs).
Table 77. Auto-Offset Hold
Select
Result
0
Disables auto-offset updates and holds the
current auto-offset values
1
Allows auto-offset to update continuously
0x2C—Bits[3:0]
Must be written to 0x0 for proper operation.
0x2D—Bits[7:0] Test Register 5
Read/write bits for future use. Must be written to 0xE8 for
proper operation.
Table 80. Auto Gain Hold
Select
Result
0
Disables auto gain updates and holds the
current auto offset values
Allows auto gain to update continuously
0x2E—Bits[7:0] Test Register 6
Read/write bits for future use. Must be written to 0xE0 for
proper operation.
1
The power-up default setting is 0.
0x34—Bit[2] SOG Filter Enable
0x3C—Bits[2:0] Auto Gain Matching Enable
This bit enables the SOG filter, which will reject inputs with a
width of less than 250 ns. This aids the PLL in the ability to
ignore extraneous (non-valid) sync pulses.
These bits enable or disable the auto gain matching function.
When set to 000, the auto gain matching function is disabled;
when set to 110 the auto gain matching function is enabled.
Table 78. SOG Filter Enable
Table 81. Auto Gain Matching Enable
Select
Result
Select
Result
0
1
SOG filter disabled
SOG filter enabled
000
110
Auto gain matching disabled
Auto gain matching enabled
Rev. PrA | Page 39 of 44
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