5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > DSP 外围设备> AD9952YSV-REEL7
AD9952YSV-REEL7 PDF预览

AD9952YSV-REEL7

更新时间： 2024-02-09 02:51:57
品牌 Logo 应用领域
亚德诺 - ADI DSP外围设备微控制器和处理器外围集成电路时钟
页数 文件大小 规格书
28页 453K
描述
400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

阅读下载

获取价格

AD9952YSV-REEL7 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：EXPOSED PAD, PLASTIC, MS-026ABC, TQFP-48
针数：48Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.2Is Samacsys：N
边界扫描：NO最大时钟频率：400 MHz
JESD-30 代码：S-PQFP-G48JESD-609代码：e0
长度：7 mm低功率模式：NO
端子数量：48最高工作温度：105 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HTFQFP封装形状：SQUARE
封装形式：FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：220
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：1.89 V最小供电电压：1.71 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：7 mm
uPs/uCs/外围集成电路类型：DSP PERIPHERAL, NUMERIC CONTROLLED OSCILLATORBase Number Matches：1

AD9952YSV-REEL7 数据手册

 浏览型号AD9952YSV-REEL7的Datasheet PDF文件第6页浏览型号AD9952YSV-REEL7的Datasheet PDF文件第7页浏览型号AD9952YSV-REEL7的Datasheet PDF文件第8页浏览型号AD9952YSV-REEL7的Datasheet PDF文件第10页浏览型号AD9952YSV-REEL7的Datasheet PDF文件第11页浏览型号AD9952YSV-REEL7的Datasheet PDF文件第12页 
AD9952  
PIN FUNCTION DESCRIPTIONS  
Table 3. 48-Lead TQFP/EP  
Pin No.  
Mnemonic  
I/O Description  
1
I/O UPDATE  
I
The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin  
must be set up and held around the SYNC_CLK output signal.  
2, 34  
3, 33, 42,  
47, 48  
DVDD  
DGND  
I
I
Digital Power Supply Pins (1.8 V).  
Digital Power Ground Pins.  
4, 6, 13,  
16, 18, 19,  
25, 27, 29  
5, 7, 14,  
15, 17, 22,  
26, 32  
AVDD  
AGND  
I
I
Analog Power Supply Pins (1.8 V).  
Analog Power Ground Pins.  
8
OSC/REFCLK  
OSC/REFCLK  
I
I
Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in single-  
ended mode, REFCLK should be decoupled to AVDD with a 0.1 µF capacitor.  
9
Reference Clock/Oscillator Input. See Clock Input section for details on the OSCILLATOR/REFCLK  
operation.  
10  
11  
CRYSTAL OUT  
CLKMODESELECT  
O
I
Output of the Oscillator Section.  
Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low, the  
oscillator section is bypassed.  
12  
LOOP_FILTER  
I
This pin provides the connection for the external zero compensation network of the REFCLK  
multiplier’s PLL loop filter. The network consists of a 1 kΩ resistor in series with a 0.1 µF capacitor  
tied to AVDD.  
20  
21  
23  
24  
IOUT  
O
O
I
Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.  
DAC Output. Should be biased through a resistor to AVDD, not AGND.  
DAC Biasline Decoupling Pin.  
A resistor (3.92 kΩ nominal) connected from AGND to DAC_RSET establishes the reference current  
for the DAC.  
IOUT  
DACBP  
DAC_RSET  
I
28  
30  
31  
35  
36  
COMP_OUT  
COMP_IN  
COMP_IN  
PWRDWNCTL  
RESET  
O
I
I
Comparator Output.  
Compator Input.  
Compartor Complementary Input  
Input Pin Used as an External Power-Down Control (see Table 8 for details).  
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9952 to the initial state,  
as described in the I/O port register map.  
I
I
37  
38  
IOSYNC  
SDO  
I
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O  
operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is  
returned low. If unused, ground this pin; do not allow this pin to float.  
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When  
operated as a 2-wire serial port, this pin is unused and can be left unconnected.  
O
39  
40  
41  
CS  
I
I
This pin functions as an active low chip select that allows multiple devices to share the I/O bus.  
This pin functions as the serial data clock for I/O operations.  
SCLK  
SDIO  
I/O When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only.  
When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.  
43  
44  
DVDD_I/O  
SYNC_IN  
I
I
Digital Power Supply (for I/O Cells Only, 3.3 V).  
Input Signal Used to Synchronize Multiple AD9952s. This input is connected to the SYNC_CLK  
output of a master AD9952.  
45  
46  
SYNC_CLK  
OSK  
O
I
Clock Output Pin that Serves as a Synchronizer for External Hardware.  
Input Pin Used to Control the Direction of the Shaped On-Off Keying Function when  
Programmed for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not  
programmed, this pin should be tied to DGND.  
<49>  
AGND  
I
The exposed paddle on the bottom of the package is a ground connection for the DAC and must  
be attached to AGND in any board layout.  
Rev. 0 | Page 9 of 28  
1...6789101112...28

下载PDF

与AD9952YSV-REEL7相关器件

型号 品牌 描述 获取价格 数据表
AD9952YSVZ ADI 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

获取价格
AD9952YSVZ-REEL7 ADI 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

获取价格
AD9953 ADI 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer

获取价格
AD9953ASV ADI 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer

获取价格
AD9953PCB ADI 400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer

获取价格
AD9953YSV ADI 400 MSPS, 14-Bit, 1.8 V CMOS Direct Digital Synthesizer

获取价格

与AD9952YSV-REEL7相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证