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AD9945KCPZRL72 PDF预览

AD9945KCPZRL72

更新时间: 2022-11-26 05:25:57
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 191K
描述
Complete 12-Bit 40 MHz CCD Signal Processor

AD9945KCPZRL72 数据手册

 浏览型号AD9945KCPZRL72的Datasheet PDF文件第10页浏览型号AD9945KCPZRL72的Datasheet PDF文件第11页浏览型号AD9945KCPZRL72的Datasheet PDF文件第12页浏览型号AD9945KCPZRL72的Datasheet PDF文件第14页浏览型号AD9945KCPZRL72的Datasheet PDF文件第15页浏览型号AD9945KCPZRL72的Datasheet PDF文件第16页 
AD9945  
Internal Power-On Reset Circuitry  
and bypass pins and their respective ground pins. All decoupling  
capacitors should be located as close as possible to the package  
pins. A single clean power supply is recommended for the AD9945,  
but a separate digital driver supply may be used for DRVDD  
(Pin 11). DRVDD should always be decoupled to DRVSS (Pin 12),  
which should be connected to the analog ground plane. Advan-  
tages of using a separate digital driver supply include using a  
lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing  
digital power dissipation, and reducing potential noise coupling.  
If the digital outputs (Pins 1 to 10, 31, and 32) must drive a  
load larger than 20 pF, buffering is recommended to reduce  
digital code transition noise. Alternatively, placing series resis-  
tors close to the digital output pins may also help reduce noise.  
After power-on, the AD9945 will automatically reset all internal  
registers and perform internal calibration procedures. This takes  
approximately 1 ms to complete. During this time, normal clock  
signals and serial write operations may occur. However, serial  
register writes will be ignored until the internal reset operation  
is completed.  
Grounding and Decoupling Recommendations  
As shown in Figure 11, a single ground plane is recommended for  
the AD9945. This ground plane should be as continuous as  
possible. This will ensure that all analog decoupling capacitors  
provide the lowest possible impedance path between the power  
3
SERIAL  
INTERFACE  
D0  
D1  
24 REFB  
23 REFT  
22 CCDIN  
1.0F  
1.0F  
D2  
D3  
D4  
1
2
3
PIN 1  
IDENTIFIER  
0.1F  
CCDIN  
21 AVSS  
20 AVDD  
D5  
D6  
D7  
D8  
4
5
6
7
AD9945  
3V  
ANALOG  
SUPPLY  
19 SHD  
0.1F  
TOP VIEW  
(Not to Scale)  
18 SHP  
D9  
8
17 CLPOB  
12  
5
CLOCK  
INPUTS  
DATA  
OUTPUTS  
3V  
DRIVER  
SUPPLY  
3V  
ANALOG  
SUPPLY  
0.1F  
0.1F  
NC = NO CONNECT  
NOTE  
THE EXPOSED PAD ON THE BOTTOM OF THE AD9945 SHOULD BE  
SOLDERED TO THE GND PLANE OF THE PRINTED CIRCUIT BOARD  
Figure 11. Recommended Circuit Configuration for CCD Mode  
REV. A  
–13–  

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