Datasheet > AD9945KCPZRL72

AD9945KCPZRL72

更新时间： 2022-11-26 05:25:57

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	191K
描述
Complete 12-Bit 40 MHz CCD Signal Processor

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中文翻译

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数据手册

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AD9945KCPZRL72 数据手册

AD9945

CCD MODE TIMING

CCD

SIGNAL

t_ID

N+1

N+2

N+9

N+10

t_ID

SHP

t_S1

t_S2

t_CP

SHD

DATACLK

t_OD

OUTPUT

DATA

N–10

N–9

N–8

N–1

NOTES

1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.

2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.

Figure 8. CCD Mode Timing

HORIZONTAL

BLANKING

EFFECTIVE PIXELS

OPTICAL BLACK PIXELS

DUMMY PIXELS

EFFECTIVE PIXELS

CCD

SIGNAL

CLPOB

PBLK

OUTPUT

DATA

EFFECTIVE PIXEL DATA

OB PIXEL DATA

DUMMY BLACK

EFFECTIVE DATA

NOTES

1. CLPOB WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING WITH CLPOB.

2. PBLK SIGNAL IS OPTIONAL.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS NINE DATACLK CYCLES.

Figure 9. Typical CCD Mode Line Clamp Timing

REV. A

–11–

1...8 9 101112 13 14...16

中文翻译

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