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AD9889BBBCZ-165 PDF预览

AD9889BBBCZ-165

更新时间: 2024-02-10 09:43:34
品牌 Logo 应用领域
亚德诺 - ADI 消费电路商用集成电路
页数 文件大小 规格书
12页 301K
描述
High Performance HDMI/DVI Transmitter

AD9889BBBCZ-165 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LFBGA, BGA76,10X10,20针数:76
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.58
Is Samacsys:N商用集成电路类型:CONSUMER CIRCUIT
JESD-30 代码:S-PBGA-B76长度:6 mm
功能数量:1端子数量:76
最高工作温度:85 °C最低工作温度:-25 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA76,10X10,20封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.8 V认证状态:Not Qualified
座面最大高度:1.4 mm子类别:Other Consumer ICs
最大供电电压 (Vsup):1.89 V最小供电电压 (Vsup):1.71 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL EXTENDED端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
Base Number Matches:1

AD9889BBBCZ-165 数据手册

 浏览型号AD9889BBBCZ-165的Datasheet PDF文件第5页浏览型号AD9889BBBCZ-165的Datasheet PDF文件第6页浏览型号AD9889BBBCZ-165的Datasheet PDF文件第7页浏览型号AD9889BBBCZ-165的Datasheet PDF文件第9页浏览型号AD9889BBBCZ-165的Datasheet PDF文件第10页浏览型号AD9889BBBCZ-165的Datasheet PDF文件第11页 
AD9889B  
Preliminary Technical Data  
Pin No.  
LFCSP  
Mnemonic Type1 Description  
BGA  
LQFP  
1, 48, 49  
1, 61, 62,  
63, 64  
D5, D6, D7, E7  
DVDD  
P
1.8 V Power Supply for Digital and I/O Power Supply. These  
pins supply power to the digital logic and I/Os. They should  
be filtered and as quiet as possible.  
15, 16, 17,  
16, 19, 20, 21  
G4, G5, J1  
PVDD  
P
1.8 V PLL Power Supply. The most sensitive portion of the  
AD9889B is the clock generation circuitry. These pins provide  
power to the clock PLL. The designer should provide quiet,  
noise-free power to these pins.  
64, paddle  
on bottom  
side  
15, 17, 18, 22,  
26, 32, 39, 42,  
43, 59, 60, 79,  
80  
D4, E4, F4, J4, G6,  
J6, K6, F7, G7, H9,  
J9  
GND  
P
Ground. The ground return for all circuitry on-chip. It is  
recommended that the AD9889B be assembled on a single,  
solid ground plane with careful attention given to ground  
current paths.  
F9  
36  
35  
47  
SDA  
SCL  
C3  
C3  
Serial Port Data I/O. This pin serves as the serial port data I/O  
slave for register access. Supports CMOS logic levels from  
1.8 V to 3.3 V.  
Serial Port Data Clock. This pin serves as the serial port data  
clock slave for register access. Supports CMOS logic levels  
from 1.8 V to 3.3 V.  
F10  
46  
E10  
E9  
37  
38  
34  
33  
48  
49  
45  
44  
MDA  
C3  
C3  
C3  
C3  
Serial Port Data I/O Master to HDCP Key EEPROM. Supports  
CMOS logic levels from 1.8 V to 3.3 V.  
Serial Port Data Clock Master to HDCP Key EEPROM. Supports  
CMOS logic levels from 1.8 V to 3.3 V.  
Serial Port Data I/O to Receiver. This pin serves as the master  
to the DDC bus. 5 V CMOS logic level.  
Serial Port Data Clock to Receiver. This pin serves as the  
master clock for the DDC bus. 5 V CMOS logic level.  
MCL  
G9  
DDCSDA  
DDCSCL  
G10  
1 I = input, O = output, P = power supply, C = control.  
2 Pin J7 (BGA), Pin 26 (LFCSP), and Pin 33 (LQFP) are dual function pins: I2C selection and power-down control. The I2C selection function occurs at power-up; the power-  
down control function occurs whenever the state of the pin is changed from its original state at power-up.  
3 For a full description of the 2-wire serial interface and its functionality obtain documentation by contacting NDA from flatpanel_apps@analog.com.  
Rev. PrA | Page 8 of 12  
 
 
 

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