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AD9889BBBCZ-165

更新时间： 2024-02-27 13:24:56

品牌	Logo	应用领域
亚德诺 - ADI		消费电路商用集成电路
页数	文件大小	规格书
12页	301K
描述
High Performance HDMI/DVI Transmitter

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技术参数
数据手册

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AD9889BBBCZ-165 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LFBGA, BGA76,10X10,20	针数：	76
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.58
Is Samacsys：	N	商用集成电路类型：	CONSUMER CIRCUIT
JESD-30 代码：	S-PBGA-B76	长度：	6 mm
功能数量：	1	端子数量：	76
最高工作温度：	85 °C	最低工作温度：	-25 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFBGA
封装等效代码：	BGA76,10X10,20	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	1.8 V	认证状态：	Not Qualified
座面最大高度：	1.4 mm	子类别：	Other Consumer ICs
最大供电电压 (Vsup)：	1.89 V	最小供电电压 (Vsup)：	1.71 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL EXTENDED	端子形式：	BALL
端子节距：	0.5 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	6 mm
Base Number Matches：	1

AD9889BBBCZ-165 数据手册

AD9889B

Preliminary Technical Data

PCB LAYOUT RECOMMENDATIONS

Other Input Signals

The AD9889B is a high precision, high speed analog device. As

such, to obtain the maximum performance from the part, it is

important to have a well laid out board.

The HPD must be connected to the HDMI connector. A 10 kΩ

pull-down resistor to ground is also recommended.

POWER SUPPLY BYPASSING

The PD/A0 input pin can be connected to GND or supply

(through a resistor or a control signal). The device address and

power-down polarity are set by the state of the PD/A0 pin when

the AD9889B supplies are applied/enabled. For example, if the

PD/A0 pin is low (when the supplies are turned on), then the

device address is 0x72 and the power-down is active high. If the

PD/A0 pin is high (when the supplies are turned on), the device

address is 0x7A and the power-down is active low.

It is recommended to bypass each power supply pin with a

0.1 μF capacitor. The exception is when two or more supply

pins are adjacent to each other. For these groupings of

powers/grounds, it is necessary to have only one bypass

capacitor. The fundamental idea is to have a bypass capacitor

within about 0.5 cm of each power pin. Also, avoid placing the

capacitor on the opposite side of the PC board from the

AD9889B, as that interposes resistive vias in the path.

The SCL and SDA pins should be connected to the I²C master.

A pull-up resistor of 2 kꢀ to 1.8 V or 3.3 V is recommended.

The bypass capacitors should be physically located between the

power plane and the power pin. Current should flow from the

power plane to the capacitor to the power pin. Do not make a

power connection between the capacitor and the power pin.

Placing a via underneath the capacitor pads, down to the power

plane, is generally the best approach.

EXTERNAL SWING RESISTOR

The external swing resistor must be connected directly to the

EXT_SWG pin and ground. The external swing resistor must

have a value of 887 Ω ( 1% tolerance). Avoid running any high

speed ac or noisy signals next to, or close to, the EXT_SWG pin.

It is particularly important to maintain low noise and good

stability of PVDD (the PLL supply). Abrupt changes in PVDD

can result in similarly abrupt changes in sampling clock phase

and frequency. This can be avoided by careful attention to

regulation, filtering, and bypassing. It is best practice to provide

separate regulated supplies for each of the analog circuitry

groups (AVDD and PVDD).

OUTPUT SIGNALS

TMDS Output Signals

The AD9889B has three TMDS data channels (0, 1, and 2) that

output signals up to 800 MHz as well as the TMDS output data

clock. To minimize the channel-to-channel skew, make the

trace length of these signals the same. Additionally, these traces

need to have a 50 ꢀ characteristic impedance and need to be

routed as 100 ꢀ differential pairs. Best practice recommends

routing these lines on the top PCB layer avoiding the use of vias.

It is also recommended to use a single ground plane for

the entire board. Experience has repeatedly shown that

the noise performance is the same or better with a single

ground plane. Using multiple ground planes can be detri-

mental because each separate ground plane is smaller, and

long ground loops can result.

Other Output Signals (non TMDS)

DDCSCL and DDCSDA

The DDCSCL and DDCSDA outputs need to have a minimum

amount of capacitance loading to ensure the best signal integrity.

The DDCSCL and DDCSDA capacitance loading must be less

than 50 pF to meet the HDMI compliance specification. The

DDCSCL and DDCSDA must be connected to the HDMI

connector and a pull-up resistor to 5 V is required. The pull-up

resistor must have a value between 1.5 kΩ and 2 kΩ.

DIGITAL INPUTS

Video and Audio Data Input Signals

The digital inputs on the AD9889B are designed to work with

signals ranging from 1.8 V to 3.3 V logic level. Therefore, no

extra components need to be added when using 3.3 V logic.

Any noise that gets onto the clock input (labeled CLK) trace

adds jitter to the system. Therefore, minimize the video clock

input (Pin 6: CLK) trace length and do not run any digital or

other high frequency traces near it. Make sure to match the

length of the input data signals to optimize data capture,

especially for high frequency modes such as 1080p and UXGA

and double data rate input formats.

INT Pin

The INT pin is an output that should be connected to the micro-

controller of the system. A pull-up resistor to 1.8 V or 3.3 V is

required for proper operation—the recommended value is 2 kΩ.

MCL and MDA

The MCL and MDA outputs should be connected to the

EEPROM containing the HDCP key (if HDCP is implemented).

Pull-up resistors of 2 kΩ are recommended.

Rev. PrA | Page 10 of 12

1...7 8 91011 12

中文翻译

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AD9889BBCPZ-80	ADI	获取价格	High Performance HDMI/DVI Transmitter
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AD9889BBSTZ-165	ROCHESTER	获取价格	SPECIALTY CONSUMER CIRCUIT, PQFP80, ROHS COMPLIANT, MS-026BEC, LQFP-80

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