AD9851
8
8
I
I/Q MIXER
AND
LOW PASS
FILTER
AD9059
DUAL
8-BIT ADC
Rx
RF IN
DIGITAL
DEMODULATOR
Rx BASEBAND
DIGITAL DATA OUT
Q
VCA
AGC
ADC CLOCK FREQUENCY
LOCKED TO
Tx CHIP/SYMBOL/PN RATE
ADC ENCODE
180MHz
OR 30MHz
AD9851
32
CLOCK
GENERATOR
CHIP/SYMBOL/PN
RATE DATA
REFERENCE
CLOCK
Figure 1. “Chip Rate” Clock Generator Application in a Spread Spectrum Receiver
LOW-PASS
IOUT
FILTER
100k⍀
100k⍀
100⍀
470pF
200⍀
200⍀
8-BIT PARALLEL DATA,
OR 1-BIT ؋
40 SERIAL DATA,
RESET, W CLK AND FQ UD
MICROPROCESSOR
7TH ORDER ELLIPTICAL
70MHz LOW PASS
200⍀ IMPEDANCE
DATA
BUS
OR
MICROCONTROLLER
IOUTB
VOLTAGE HERE = CENTER POINT
OF SINE WAVE (0.5V TYPICALLY)
AD9851
0 TO 1V p-p
SINE WAVE
180MHz OR 30MHz
REFERENCE
CLOCK
USING PASSIVE "AVERAGING" CIRCUIT
CMOS
OUTPUTS
QOUT
QOUTB
R
SET
3.9k⍀
Figure 2. Basic Clock Generator Configuration
REFERENCE
Both IOUT and IOUTB are equally loaded with 100 Ω. Two
100 kΩ resistors “sample” each output and average the two
voltages. The result is filtered with the 470 pF capacitor and
applied to one comparator input as a dc switching threshold.
The filtered DAC sine wave output is applied to the other com-
parator input. The comparator will toggle with nearly 50% duty
cycle as the sine wave alternately traverses the “center point”
threshold.
CLOCK
RF
PHASE
COMPARATOR
LOOP
FILTER
FREQUENCY
VCO
OUT
FILTER
REF CLK IN
AD9851
DDS
PROGRAMMABLE
"DIVIDE-BY-N" FUNCTION
32
(WHERE N = 2 /TUNING WORD)
TUNING
WORD
RF
IF FREQUENCY
FILTER
FREQUENCY
OUT
IN
Figure 5. Digitally-Programmable “Divide-by-N” Function
in PLL
FILTER
REFERENCE
CLOCK
AD9851/FSPCB
8-BIT
EVALUATION
BOARD
ADSP-2181
BUS
DATA
BUS
AD9851
DDS
TUNING
WORD
EZ-KIT LITE
DSP
DAC
OUT
INPUT/
ADSP-2181
DSP
PROCESSOR
OUTPUT
DECODE
LOGIC
AD9851
DDS
FM RF
OUTPUT
Figure 3. Frequency/Phase-Agile Local Oscillator for
Frequency Mixing/Multiplying
REF
OSC
AD1847
L & R
AUDIO IN
STEREO
REFERENCE
CLOCK
CODEC
AD9851
DDS
TUNING
WORD
Figure 6. High Quality, All-Digital RF Frequency Modulation
FILTER
High quality, all digital RF frequency modulation generation
with the ADSP-2181 DSP and the AD9851 DDS. This applica-
tion is well documented in Analog Devices’ application Note
AN-543, and uses an “image” of the DDS output as illustrated
in Figure 8.
RF
PHASE
LOOP
FILTER
FREQUENCY
OUT
VCO
COMPARATOR
DIVIDE-BY-N
Figure 4. Frequency/Phase-Agile Reference for PLL
–6–
REV. C