AD9851
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
4–1,
28–25
5
6
7
D0–D7
8-Bit Data Input. The data port for loading the 32-bit frequency and 8-bit phase/control words. D7 = MSB;
D0 = LSB. D7, Pin 25, also serves as the input pin for 40-bit serial data word.
6× REFCLK Multiplier Ground Connection.
6× REFCLK Multiplier Positive Supply Voltage Pin.
Word Load Clock. Rising edge loads the parallel or serial frequency/phase/control words asynchronously
into the 40-bit input register.
PGND
PVCC
W_CLK
8
9
FQ_UD
Frequency Update. A rising edge asynchronously transfers the contents of the 40-bit input register to be
acted upon by the DDS core. FQ_UD should be issued when the contents of the input register are known
to contain only valid, allowable data.
REFCLOCK Reference Clock Input. CMOS/TTL-level pulse train, direct or via the 6× REFCLK Multiplier. In direct
mode, this is also the SYSTEM CLOCK. If the 6× REFCLK Multiplier is engaged, then the output of the
multiplier is the SYSTEM CLOCK. The rising edge of the SYSTEM CLOCK initiates operations.
10, 19
11, 18
AGND
AVDD
Analog Ground. The ground return for the analog circuitry (DAC and Comparator).
Positive supply voltage for analog circuitry (DAC and Comparator, Pin 18) and bandgap voltage reference,
Pin 11.
12
RSET
The DAC’s external RSET connection—nominally a 3.92 kΩ resistor to ground for 10 mA out. This sets
the DAC full-scale output current available from IOUT and IOUTB. RSET = 39.93/IOUT
13
14
15
16
17
VOUTN
VOUTP
VINN
VINP
DACBP
Voltage Output Negative. The comparator’s “complementary” CMOS logic level output.
Voltage Output Positive. The comparator’s “true” CMOS logic level output.
Voltage Input Negative. The comparator’s inverting input.
Voltage Input Positive. The comparator’s noninverting input.
DAC Bypass Connection. This is the DAC voltage reference bypass connection normally NC (NO
CONNECT) for optimum SFDR performance.
20
21
22
IOUTB
IOUT
The “complementary” DAC output with same characteristics as IOUT except that IOUTB = (full-scale
output–IOUT). Output load should equal that of IOUT for best SFDR performance.
The “true” output of the balanced DAC. Current is “sourcing” and requires current-to-voltage
conversion, usually a resistor or transformer referenced to GND. IOUT = (full-scale output–IOUTB)
RESET
Master Reset pin; active high; clears DDS accumulator and phase offset register to achieve 0 Hz and 0°
output phase. Sets programming to parallel mode and disengages the 6× REFCLK Multiplier. Reset does
not clear the 40-bit input register. On power-up, asserting RESET should be the first priority before pro-
gramming commences.
23
24
DVDD
DGND
Positive supply voltage pin for digital circuitry.
Digital Ground. The ground return pin for the digital circuitry.
PIN CONFIGURATION
1
2
28
27
26
25
24
23
22
21
20
19
18
D3
D2
D4
D5
D1
3
D6
LSB D0
PGND
4
D7 MSB/SERIAL LOAD
5
DGND
DVDD
RESET
IOUT
6
PVCC
AD9851
TOP VIEW
(Not to Scale)
7
W CLK
FQ UD
REFCLOCK
AGND
AVDD
8
9
IOUTB
AGND
AVDD
10
11
12
13
14
17 DACBP
16 VINP
R
SET
VOUTN
VOUTP
15
VINN
REV. C
–5–