AD9851
Test
Level
AD9851BRS
Typ
Parameter
Temp
Min
Max
Units
TIMING CHARACTERISTICS4
tWH, tWL (W_CLK Min Pulsewidth High/Low)
tDS, tDH (Data to W_CLK Setup and Hold Times)
tFH, tFL (FQ_UD Min Pulsewidth High/Low)
tCD (REFCLK Delay After FQ_UD)5
tFD (FQ_UD Min Delay After W_CLK)
tCF (Output Latency from FQ_UD)
Frequency Change
FULL
FULL
FULL
FULL
FULL
IV
IV
IV
IV
IV
3.5
3.5
7
3.5
7
ns
ns
ns
ns
ns
FULL
FULL
IV
IV
18
13
SYSCLK
Cycles
SYSCLK
Cycles
ns
Phase Change
tRH (CLKIN Delay After RESET Rising Edge)
tRL (RESET Falling Edge After CLKIN)
tRR (Recovery from RESET)
FULL
FULL
FULL
IV
IV
IV
3.5
3.5
2
ns
SYSCLK
Cycles
SYSCLK
Cycles
SYSCLK
Cycles
µs
tRS (Minimum RESET Width)
FULL
FULL
+25°C
IV
IV
V
5
tOL (RESET Output Latency)
13
Wake-Up Time from Power-Down Mode6
5
CMOS LOGIC INPUTS
Logic “1” Voltage, +5 V Supply
Logic “1” Voltage, +3.3 V Supply
Logic “1” Voltage, +2.7 V Supply
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Rise/Fall Time
Input Capacitance
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
I
I
I
I
I
I
IV
V
3.5
3.0
2.4
V
V
V
V
µA
µA
ns
pF
0.4
12
12
100
3
POWER SUPPLY
VS6 Current @:
62.5 MHz Clock, +2.7 V Supply
100 MHz Clock, +2.7 V Supply
62.5 MHz Clock, +3.3 V Supply
125 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +5 V Supply
125 MHz Clock, +5 V Supply
180 MHz Clock, +5 V Supply
Power Dissipation @ :
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
VI
VI
VI
VI
VI
VI
VI
30
40
35
55
50
70
110
35
50
45
70
65
90
130
mA
mA
mA
mA
mA
mA
mA
62.5 MHz Clock, +5 V Supply
62.5 MHz Clock, +3.3 V Supply
62.5 MHz Clock, +2.7 V Supply
100 MHz Clock, +2.7 V Supply
125 MHz Clock, +5 V Supply
125 MHz Clock, +3.3 V Supply
180 MHz Clock, +5 V Supply
PDISS Power-Down Mode @:
+5 V Supply
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
VI
VI
VI
VI
VI
VI
VI
250
115
85
110
365
180
555
325
150
95
135
450
230
650
mW
mW
mW
mW
mW
mW
mW
+25°C
+25°C
VI
VI
17
4
55
20
mW
mW
+2.7 V Supply
NOTES
1+VS collectively refers to the positive voltages applied to DVDD, PVCC and AVDD. Voltages applied to these pins should be of the same potential.
2Indicates the minimum signal levels required to reliably clock the device at the indicated supply voltages. This specifies the p-p signal level and dc offset needed when
the clocking signal is not of CMOS/TTL origin, i.e., a sine wave with 0 V dc offset.
3The comparator’s jitter contribution to any input signal. This is the minimum jitter on the outputs that can be expected from an ideal input. Considerably more
output jitter is seen when nonideal input signals are presented to the comparator inputs. Nonideal characteristics include the presence of extraneous, nonharmonic
signals (spur’s, noise), slower slew rate and low comparator overdrive.
4Timing of input signals FQ_UD, WCLK, RESET are asynchronous to the Reference Clock; however, the presence of a Reference Clock is required to implement
those functions. In the absence of a Reference Clock, the AD9851 automatically enters power-down mode rendering the IC, including the comparator, inoperable
until a Reference Clock is restored. Very high speed updates of frequency/phase word will require FQ_UD and WCLK to be externally synchronized with the exter-
nal Reference Clock to assure proper timing.
5Not applicable when 6× REFCLK Multiplier is engaged.
6Assumes no capacitive load on DACBP (Pin 17).
Specifications subject to change without notice.
REV. C
–3–