Datasheet > AD9821

AD9821

更新时间： 2024-02-17 11:53:47

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
16页	269K
描述
Complete 12-Bit 40 MSPS Imaging Signal Processor

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AD9821 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	1.40 MM, PLASTIC, MS-026BBC, LQFP-48	针数：	48
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	5.8
最大模拟输入电压：	1.8 V	最小模拟输入电压：
转换器类型：	ADC, PROPRIETARY METHOD	JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e3	长度：	7 mm
湿度敏感等级：	3	模拟输入通道数量：	1
位数：	12	功能数量：	1
端子数量：	48	最高工作温度：	85 °C
最低工作温度：	-20 °C	输出位码：	BINARY
输出格式：	PARALLEL, WORD	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP48,.35SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	3 V
认证状态：	Not Qualified	采样速率：	40 MHz
采样并保持/跟踪并保持：	SAMPLE	座面最大高度：	1.6 mm
子类别：	Other Converters	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	7 mm

AD9821 数据手册

AD9821

Variable Gain Amplifier

programmed using the 8-bit Clamp Level Register. The resulting

error signal is filtered to reduce noise, and the correction value is

applied to the ADC input through a D/A converter. Normally, the

optical black clamp loop is turned on once per horizontal line, but

this loop can be updated more slowly to suit a particular

application. If external digital clamping is used during the post-

processing, the AD9821 optical black clamping may be disabled

using Bit D5 in the Operation Register (see Internal Register

Map and Serial Interface Timing section). When the loop is

disabled, the Clamp Level Register may still be used to provide

programmable offset adjustment.

The VGA stage provides a gain range of 0 dB to 36 dB, program-

mable with 10-bit resolution through the serial digital interface. A

minimum gain of 6 dB is needed to match a 1 V input signal with

the ADC full-scale range of 2 V. When compared to 1 V full-scale

systems, the equivalent gain range is –6 dB to +30 dB.

The VGA gain curve follows a “linear-in-dB” characteristic.

The exact VGA gain can be calculated for any Gain Register

value by using the equation:

Gain(dB) = (0.0351× Code)

where the code range is 0 to 1023.

Horizontal timing is shown in Figure 9. The CLPOB pulse

should be placed during the CCD’s optical black pixels. It is

recommended that the CLPOB pulse duration be at least 20

pixels wide. Shorter pulsewidths may be used, but the ability to

track low frequency variations in the black level will be reduced.

As discussed in the Differential Input SHA section, the CLPOB

loop is capable of correcting for an offset difference between the

VIN+ and VIN– inputs. Because the clamp is located after the

VGA gain stage, the clamp will be most limited when the VGA

gain is at its maximum value. Under these conditions, the OB

clamp loop correction range is restricted to 30 mV offset

between the VIN+ and VIN– inputs. At minimum VGA gain,

the offset correction range increases to 250 mV of offset. If the

OB clamp loop’s correction range is exceeded, then the black

level at the output of the AD9821 will increase and further

correction will be necessary. As mentioned previously, it is also

possible to disable the AD9821’s OB clamp loop.

127

255

383

511

639

767

895

1023

VGA GAIN REGISTER CODE

Figure 11. VGA Gain Curve

Optical Black Clamp

A/D Converter (ADC)

The AD9821 uses high performance ADC architecture, opti-

mized for high speed and low power. Differential nonlinearity

(DNL) performance is typically better than 0.5 LSB, as shown in

TPC 2. Instead of the 1 V full-scale range used by the earlier

AD9801 and AD9803 products from Analog Devices, the

AD9821’s ADC uses a 2 V input range. Better noise performance

results from using a larger ADC full-scale range (see TPC 3).

The optical black clamp loop is used to remove residual offsets

in the signal chain, and to track low frequency variations in the

CCD’s black level. During the optical black (shielded) pixel

interval on each line, the ADC output is compared with a fixed

black level reference selected by the user in the Clamp Level

–12–

REV. 0

1...9 10 111213 14 15 16

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与AD9821相关器件

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AD9821KST	ADI	Complete 12-Bit 40 MSPS Imaging Signal Processor	获取价格
AD9822	ADI	Complete 14-Bit CCD/CIS Signal Processor	获取价格
AD9822JR	ADI	Complete 14-Bit CCD/CIS Signal Processor	获取价格
AD9822JRRL	ADI	Complete 14-Bit CCD/CIS Signal Processor	获取价格
AD9822JRS	ADI	Complete 14-Bit CCD/CIS Signal Processor	获取价格
AD9822JRSRL	ADI	Complete 14-Bit CCD/CIS Signal Processor	获取价格

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