16-Bit, 160 MSPS 2x/4x/8x
Interpolating Dual TxDAC+® D/A Converter
AD9777
Versatile input data interface
FEATURES
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
16-bit resolution, 160 MSPS/400 MSPS input/output
data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI® port
Power dissipation: typical 1.2 W @ 3.3 V
On-chip 1.2 V reference
80-lead thin quad flat package, exposed pad (TQFP_EP)
APPLICATIONS
Communications
Excellent ac performance
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
SFDR −73 dBc @ 2 MHz to 35 MHz
WCDMA ACPR 71 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or
TTL/CMOS/LVPECL compatible
FUNCTIONAL BLOCK DIAGRAM
IDAC
COS
AD9777
HALF-
BAND
FILTER1*
HALF-
BAND
HALF-
BAND
GAIN
DAC
OFFSET
DAC
FILTER2* FILTER3*
DATA
SIN
fDAC/2, 4, 8
SIN
ASSEMBLER
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
16
16
16
16
16
16
I
I/Q DAC
GAIN/OFFSET
REGISTERS
LATCH
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
16
16
16
Q
LATCH
16
FILTER
BYPASS
MUX
COS
WRITE
MUX
CONTROL
I
IDAC
SELECT
OUT
/2
(fDAC)
CLOCK OUT
/2
/2
/2
SPI INTERFACE AND
CONTROL REGISTERS
PRESCALER
DIFFERENTIAL
CLK
PHASE DETECTOR
AND VCO
* HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
Figure 1.
Rev. C
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