14-Bit, 2.0 GSPS/2.6 GSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9689
Data Sheet
0.975 V, 1.9 V, and 2.5 V dc supply operation
FEATURES
9 GHz analog input full power bandwidth (−3 dB)
Amplitude detect bits for efficient AGC implementation
Programmable FIR filters for analog channel loss equalization
2 integrated, wideband digital processors per channel
JESD204B (Subclass 1) coded serial digital outputs
Support for lane rates up to 16 Gbps per lane
Noise density
−152 dBFS/Hz at 2.56 GSPS at full-scale voltage = 1.7 V p-p
−154 dBFS/Hz at 2.56 GSPS at full-scale voltage = 2.0 V p-p
−154.2 dBFS/Hz at 2.0 GSPS at full-scale voltage = 1.7 V p-p
−155.3 dBFS/Hz at 2.0 GSPS at full-scale voltage = 2.0 V p-p
1.55 W total power per channel at 2.56 GSPS (default settings)
SFDR at 2.56 GSPS encode
48-bit NCO
Programmable decimation rates
Phase coherent NCO switching
Up to 4 channels available
Serial port control
Supports 100 MHz SPI writes and 50 MHz SPI reads
Integer clock with divide by 2 and divide by 4 options
Flexible JESD204B lane configurations
On-chip dither
73 dBFS at 1.8 GHz AIN at −2.0 dBFS
59 dBFS at 5.53 GHz AIN at −2.0 dBFS
full-scale voltage = 1.1 V p-p
SNR at 2.56 GSPS encode
59.7 dBFS at 1.8 GHz AIN at −2.0 dBFS
53.0 dBFS at 5.53 GHz AIN at −2.0 dBFS
full-scale voltage = 1.1 V p-p
APPLICATIONS
Diversity multiband and multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A
Electronic test and measurement systems
Phased array radar and electronic warfare
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
SFDR at 2.0 GSPS encode
78 dBFS at 900 MHz AIN at −2.0 dBFS
62 dBFS at 5.53 GHz AIN at −2.0 dBFS
full-scale voltage = 1.1 V p-p
SNR at 2.0 GSPS encode
62.7 dBFS at 900 MHz AIN at −2.0 dBFS
53.1 dBFS at 5.5 GHz AIN at −2.0 dBFS
full-scale voltage = 1.1 V p-p
FUNCTIONAL BLOCK DIAGRAM
AVDD1
(0.975V)
AVDD2
(1.9V)
AVDD3 AVDD1_SR
DVDD
DRVDD1 DRVDD2 SPIVDD
(2.5V)
(0.975V)
(0.975V)
(0.975V)
(1.9V)
(1.9V)
BUFFER
14
VIN+A
VIN–A
ADC
CORE
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SERDOUT4±
SERDOUT5±
SERDOUT6±
SERDOUT7±
DIGITAL DOWN-
CONVERTER
JESD204B
8
LINK
AND
FAST
SIGNAL
DETECT
MONITOR
Tx
DIGITAL DOWN-
CONVERTER
OUTPUTS
14
VIN+B
VIN–B
ADC
CORE
BUFFER
VREF
SYNCINB±
PDWN/STBY
JESD204B
CLOCK
DISTRIBUTION
FD_A/GPIO_A0
SUBCLASS 1
CONTROL
SYSREF±
CLK+
GPIO_A1
GPIO MUX
FD_B/GPIO_B0
GPIO_B1
SPI AND
CONTROL
REGISTERS
CLK–
÷2
÷4
AD9689
AGND
SDIO SCLK CSB
DRGND
DGND
Figure 1.
Rev. A
Document Feedback
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Trademarks and registeredtrademarks arethe property of their respective owners.
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Technical Support
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www.analog.com
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