AD9683
Data Sheet
AD9683-170
AD9683-250
Parameter1
Temperature
Min
Typ
Max
Min
Typ
Max
Unit
TWO-TONE SFDR
fIN1 = 184.12 MHz (−7 dBFS), fIN2 = 187.12 MHz (−7 dBFS)
FULL POWER BANDWIDTH2
25°C
25°C
87
87
dBc
1000
1000
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation for a complete set of definitions.
2 Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p
full-scale input range, DCS enabled, default SPI, unless otherwise noted.
Table 3.
Parameter
Temperature
Min
Typ
Max
Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Input CLK± Clock Rate
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Full
40
625
MHz
CMOS/LVDS/LVPECL
0.±
Full
Full
Full
Full
Full
Full
Full
Full
V
V p-p
V
0.3
AGND
0.±
0
−60
3.6
AVDD
1.4
+60
0
V
µA
µA
pF
kΩ
4
10
Input Resistance
8
12
RF CLOCK INPUT (RFCLK)
RF Clock Rate
Full
625
1500
MHz
Logic Compliance
Internal Bias
Input Voltage Range
CMOS/LVDS/LVPECL
0.±
Full
Full
Full
Full
Full
Full
Full
Full
V
AGND
1.2
AGND
0
AVDD
AVDD
0.6
V
V
V
High Input Voltage Level
Low Input Voltage Level
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance (AC-Coupled)
SYNCIN INPUTS (SYNCINB+/SYNCINB−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
+150
0
µA
µA
pF
kΩ
−150
1
10
8
12
CMOS/LVDS
0.±
Full
Full
Full
Full
Full
Full
Full
Full
V
0.3
DGND
0.±
−5
−10
3.6
DVDD
1.4
V p-p
V
V
+5
+10
µA
µA
pF
kΩ
1
16
Input Resistance
12
20
Rev. 0 | Page 6 of 44