14-Bit, 500 MSPS LVDS,
Dual Analog-to-Digital Converter
Data Sheet
AD9684
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD1
(1.25V)
AVDD2
(2.5V)
AVDD3
(3.3V)
DVDD
DRVDD
(1.25V)
SPIVDD
Parallel LVDS (DDR) outputs
(1.25V)
(1.8V TO 3.4V)
1.1 W total power per channel at 500 MSPS (default settings)
SFDR = 85 dBFS at 170 MHz fIN (500 MSPS)
SNR = 68.6 dBFS at 170 MHz fIN (500 MSPS)
ENOB = 10.9 bits at 170 MHz fIN
DNL = ±0.5 LSB
INL = ±±.5 LSB
Noise density = −153 dBFS/Hz at 500 MSPS
1.±5 V, ±.50 V, and 3.3 V supply operation
No missing codes
BUFFER
VIN+A
VIN–A
14
D0±
ADC
D1±
CORE
D2±
DIGITAL
DOWN-
D3±
D4±
CONVERTER
D5±
16
FD_A
FD_B
D6±
D7±
D8±
D9±
D10±
D11±
D12±
D13±
DCO±
STATUS±
DIGITAL
DOWN-
CONVERTER
BUFFER
VIN+B
VIN–B
14
ADC
CORE
CONTROL
REGISTERS
Internal analog-to-digital converter (ADC) voltage reference
Flexible input range and termination impedance
1.46 V p-p to ±.06 V p-p (±.06 V p-p nominal)
400 Ω, ±00 Ω, 100 Ω, and 50 Ω differential
SYNC± input allows multichip synchronization
DDR LVDS (ANSI-644 levels) outputs
± GHz usable analog input full power bandwidth
>96 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
Two integrated wideband digital processors per channel
1±-bit numerically controlled oscillator (NCO)
3 cascaded half-band filters
FAST
DETECT
V_1P0
SYNC+
SYNC–
SIGNAL MONITOR
CLOCK
GENERATION
CLK+
CLK–
SPI CONTROL
÷2
÷4
÷8
PDWN/
STBY
AD9684
DGND
AGND DRGND
SDIO
SCLK CSB
Figure 1.
GENERAL DESCRIPTION
The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has
an on-chip buffer and a sample-and-hold circuit designed for
low power, small size, and ease of use. This product is designed
for sampling wide bandwidth analog signals. The AD9684 is
optimized for wide input bandwidth, a high sampling rate,
excellent linearity, and low power in a small package.
Differential clock inputs
Serial port control
Integer clock divide by ±, 4, or 8
Small signal dither
APPLICATIONS
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth buffered inputs, supporting a
variety of user selectable input ranges. An integrated voltage
reference eases design considerations. Each ADC data output is
internally connected to an optional decimate by 2 block.
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE
General-purpose software radios
Ultrawideband satellite receiver
Instrumentation (spectrum analyzers, network analyzers,
integrated RF test solutions)
Radar
Digital oscilloscopes
High speed data acquisition systems
DOCSIS CMTS upstream receiver paths
HFC digital reverse path receivers
The analog input and clock signals are differential inputs. Each
ADC data output is internally connected to two digital
downconverters (DDCs). Each DDC consists of four cascaded
signal processing stages: a 12-bit frequency translator (NCO),
and three half-band decimation filters supporting a divide by
factor of two, four, and eight.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 0±06±-9106, U.S.A.
Tel: 781.3±9.4700
Technical Support
©±015 Analog Devices, Inc. All rights reserved.
www.analog.com
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