Datasheet > AD9650BCPZ-25

AD9650BCPZ-25

更新时间： 2024-02-07 03:10:00

品牌	Logo	应用领域
亚德诺 - ADI		转换器
页数	文件大小	规格书
44页	1640K
描述
16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)

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AD9650BCPZ-25 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC64,.35SQ,20	针数：	64
Reach Compliance Code：	compliant	ECCN代码：	3A991.C.4
HTS代码：	8542.39.00.01	风险等级：	1.7
最大模拟输入电压：	2.7 V	最小模拟输入电压：	-2.7 V
最长转换时间：	0.05 µs	转换器类型：	ADC, FLASH METHOD
JESD-30 代码：	S-XQCC-N64	JESD-609代码：	e3
长度：	9 mm	最大线性误差 (EL)：	0.0046%
湿度敏感等级：	3	模拟输入通道数量：	2
位数：	16	功能数量：	1
端子数量：	64	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出位码：	OFFSET BINARY, 2'S COMPLEMENT BINARY, GRAY CODE
输出格式：	PARALLEL, WORD	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC64,.35SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.8 V
认证状态：	Not Qualified	采样速率：	25 MHz
采样并保持/跟踪并保持：	SAMPLE	座面最大高度：	1 mm
子类别：	Analog to Digital Converters	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	9 mm	Base Number Matches：	1

AD9650BCPZ-25 数据手册

16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS,

1.8 V Dual Analog-to-Digital Converter (ADC)

AD9650

FUNCTIONAL BLOCK DIAGRAM

FEATURES

SDIO/ SCLK/

1.8 V analog supply operation

1.8 V CMOS or LVDS output supply

SNR

AVDD

CSB

DRVDD

DCS

DFS

SPI

AD9650

82 dBFS at 30 MHz input and 105 MSPS data rate

83 dBFS at 9.7 MHz input and 25 MSPS data rate

SFDR

90 dBc at 30 MHz input and 105 MSPS data rate

95 dBc at 9.7 MHz input and 25 MSPS data rate

Low power

328 mW per channel at 105 MSPS

119 mW per channel at 25 MSPS

Integer 1-to-8 input clock divider

IF sampling frequencies to 300 MHz

Analog input range of 2.7 V p-p

Optional on-chip dither

ORA

PROGRAMMING DATA

CMOS/LVDS

D15A (MSB)

D0A (LSB)

VIN+A

VIN–A

ADC

OUTPUT BUFFER

CLK+

CLK–

DIVIDE 1

TO 8

VREF

SENSE

DCOA

DCOB

DUTY CYCLE

STABILIZER

DCO

GENERATION

REF

SELECT

VCM

RBIAS

VIN–B

VIN+B

ORB

D15B (MSB)

D0B (LSB)

CMOS/LVDS

OUTPUT BUFFER

ADC

Integrated ADC sample-and-hold inputs

Differential analog inputs with 500 MHz bandwidth

ADC clock duty cycle stabilizer

MULTICHIP

SYNC

AGND

SYNC

PDWN

OEB

NOTES

APPLICATIONS

1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;

SEE FIGURE 7 FOR LVDS PIN NAMES.

Industrial instrumentation

Figure 1.

X-Ray, MRI, and ultrasound equipment

High speed pulse acquisition

Chemical and spectrum analysis

Direct conversion receivers

Multimode digital receivers

Flexible power-down options allow significant power savings,

when desired.

Programming for setup and control is accomplished using a 3-wire

SPI-compatible serial interface.

Smart antenna systems

General-purpose software radios

The AD9650 is available in a 64-lead LFCSP and is specified over

the industrial temperature range of −40°C to +85°C.

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/

105 MSPS analog-to-digital converter (ADC) designed for

digitizing high frequency, wide dynamic range signals with

input frequencies of up to 300 MHz.

1. On-chip dither option for improved SFDR performance

with low power analog input.

2. Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 300 MHz.

3. Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating 1.8 V CMOS or

LVDS outputs.

4. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding), enabling

the clock DCS, power-down, and test modes.

The dual ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth, differential sample-and-hold

analog input amplifiers, and shared integrated voltage reference,

which eases design considerations. A duty cycle stabilizer is

provided to compensate for variations in the ADC clock duty

cycle, allowing the converters to maintain excellent performance.

5. Pin compatible with the AD9268 and other dual families,

AD9269, AD9251, AD9231, and AD9204. This allows a

simple migration across resolutions and bandwidth.

The ADC output data can be routed directly to the two external

16-bit output ports or multiplexed on a single 16-bit bus. These

outputs can be set to either 1.8 V CMOS or LVDS.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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与AD9650BCPZ-25相关器件

型号	品牌	获取价格	描述	数据表
AD9650BCPZ-65	ADI	获取价格	16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650BCPZ-80	ADI	获取价格	16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650BCPZRL7-105	ADI	获取价格	16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650BCPZRL7-25	ADI	获取价格	16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650BCPZRL7-65	ADI	获取价格	16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650BCPZRL7-80	ADI	获取价格	16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650-EP	ADI	获取价格	Dual 16-Bit, 105 MSPS, 1.8 V Analog-to-Digital Converter
AD9650USVZ-105EP	ADI	获取价格	16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
AD9650USVZR7-105EP	ADI	获取价格	Dual 16-Bit, 105 MSPS, 1.8 V Analog-to-Digital Converter
AD9652	ADI	获取价格	Analog-to-Digital Converter (ADC)

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