Datasheet > AD9578BCPZ

AD9578BCPZ

更新时间： 2022-02-26 12:14:43

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
44页	817K
描述
Dual PLL Precision Synthesizer

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获取价格

数据手册

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AD9578BCPZ 数据手册

AD9578

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Duty Cycle (20% to 80%)

330 Ω Pull-Down Resistor

3.3 kΩ Pull-Down Resistor

C_LOAD= 10 pF

At minimum output frequency; outputs terminated

50 Ω to V_DD/2

Output Voltage High (V_OH

)

V_DD= 3.3 V

V_DD= 2.5 V

3.0

1.9

3.1

2.0

3.35

2.1

At minimum output frequency; outputs terminated

50 Ω to V_DD/2

Output Voltage Low (V_OL

)

V_DD= 3.3 V

V_DD= 2.5 V

0.22

0.2

0.32

0.3

0.42

0.4

OUTPUT TIMING SKEW

LVPECL

OUTPUT2 lags OUTPUT1; OUTPUT3 lags OUTPUT4

Between OUTPUT1 and OUTPUT2

Drivers

LVPECL mode on both drivers; rising edge only;

any divide value

Between OUTPUT3 and OUTPUT4

Drivers

LVPECL mode on both drivers; rising edge only;

any divide value

102

LVDS

Between OUTPUT1 and OUTPUT2

Drivers

LVDS mode on both drivers; rising edge only;

any divide value

Between OUTPUT3 and OUTPUT4

Drivers

LVDS mode on both drivers; rising edge only;

any divide value

100

HCSL

Between OUTPUT1 and OUTPUT2

Drivers

HCSL mode on both drivers; rising edge only;

any divide value

Between OUTPUT3 and OUTPUT4

Drivers

HCSL mode on both drivers; rising edge only;

any divide value

LVCMO S

Between OUTPUT1 and OUTPUT2

Drivers

LVCMOS mode on both drivers; rising edge only;

any divide value

Between OUTPUT3 and OUTPUT4

Drivers

LVCMOS mode on both drivers; rising edge only;

any divide value

Rev. B | Page 8 of 44

1...5 6 789 10 11...44

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