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AD9578BCPZ PDF预览

AD9578BCPZ

更新时间: 2022-02-26 12:14:43
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
44页 817K
描述
Dual PLL Precision Synthesizer

AD9578BCPZ 数据手册

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AD9578  
Data Sheet  
DISTRIBUTION CLOCK OUTPUTS(INCLUDING REFOUT/  
)
REFOUT  
Table 6.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
VDD = 3.3V ; 50 Ω to VDD − 2 V termination at output  
pins  
3.3 V LVPECL MO DE  
Output Frequency  
11.8  
919  
MHz  
REFOUT/  
limited to 60 MHz  
REFOUT  
Rise Time (20% to 80%)  
Fall Time (80% to 20%)  
130  
142  
183  
203  
ps  
ps  
Duty Cycle, OUTPUT1 and OUTPUT4  
111.8 ≤ fOUT ≤ 357 MHz  
50  
43  
46  
52  
47  
50  
54  
51  
54  
%
%
%
Output divider settings other than 4.5  
Output divider settings other than 4.5  
Measured at 765 MHz  
357 < fOUT ≤ 919 MHz  
Output Divider = 4.5  
Duty Cycle, OUTPUT2 and OUTPUT3  
111.8 ≤ fOUT ≤ 357 MHz  
49  
51  
53  
%
Output divider settings other than 4.5  
Output divider settings other than 4.5  
357 < fOUT ≤ 919 MHz  
45  
49  
51  
%
Output Divider = 4.5  
51  
57  
63  
%
Measured at 765 MHz  
Voltage across pins at minimum output frequency; if  
a differential probe is used, peak-to-peak voltage (VPP)  
is 2× this value  
Differential Output Voltage Swing  
700  
850  
1000  
mV  
Common-Mode Output Voltage  
2.5 V LVPECL MODE  
1.81  
11.8  
1.91  
2.01  
V
VDD = 2.5 V; 50 Ω to VDD − 2 V termination at output  
pins  
Output Frequency  
919  
MHz  
REFOUT/  
limited to 60 MHz  
REFOUT  
Rise Time (20% to 80%)  
Fall Time (80% to 20%)  
137  
148  
186  
209  
ps  
ps  
Duty Cycle, OUTPUT1 and OUTPUT4  
111.8 ≤ fOUT ≤ 357 MHz  
50  
49  
46  
52  
51  
50  
54  
54  
54  
%
%
%
Output divider settings other than 4.5  
Output divider settings other than 4.5  
Measured at 765 MHz  
357 < fOUT ≤ 919 MHz  
Output Divider = 4.5  
Duty Cycle, OUTPUT2 and OUTPUT3  
111.8 ≤ fOUT ≤ 357 MHz  
43  
48  
51  
%
Output divider settings other than 4.5  
Output divider settings other than 4.5  
357 < fOUT ≤ 919 MHz  
44  
48  
52  
%
Output Divider = 4.5  
51  
57  
63  
%
Measured at 765 MHz  
Voltage across pins at minimum output frequency; if  
a differential probe is used, VPP is 2× this value  
Differential Output Voltage Swing  
700  
850  
1000  
mV  
Common-Mode Output Voltage  
3.3 V HCSL MODE  
1.05  
11.8  
1.15  
1.25  
V
50 Ω to ground termination at output pins  
Output Frequency  
919  
MHz  
REFOUT/  
limited to 60 MHz  
REFOUT  
Rise Time (20% to 80%)  
Fall Time (80% to 20%)  
Duty Cycle, OUTPUT1 and OUTPUT4  
111.8 ≤ fOUT ≤ 357 MHz  
357 < fOUT ≤ 919 MHz  
180  
186  
266  
286  
ps  
ps  
51  
48  
49  
52  
51  
52  
54  
54  
56  
%
%
%
Output divider settings other than 4.5  
Output divider settings other than 4.5  
Measured at 765 MHz  
Output Divider = 4.5  
Duty Cycle, OUTPUT2 and OUTPUT3  
111.8 ≤ fOUT ≤ 357 MHz  
357 < fOUT ≤ 919 MHz  
50  
53  
51  
59  
750  
0
54  
%
Output divider settings other than 4.5  
Output divider settings other than 4.5  
Measured at 765 MHz  
48  
53  
%
Output Divider = 4.5  
53  
67  
%
Output High Voltage  
624  
−50  
624  
850  
+50  
850  
mV  
mV  
mV  
Output Low Voltage  
Voltage across pins at minimum output frequency;  
when a differential probe is used, VPP is 2× this value  
Output Voltage Swing (VSWING  
)
750  
Absolute Crossing Point (VOX  
)
295  
360  
14  
400  
17  
mV  
mA  
Short-Circuit Output Current  
Rev. B | Page 6 of 44  

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