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AD9578BCPZ PDF预览

AD9578BCPZ

更新时间: 2022-02-26 12:14:43
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
44页 817K
描述
Dual PLL Precision Synthesizer

AD9578BCPZ 数据手册

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Data Sheet  
AD9578  
LOGICINPUTS ( , , OEREF, OE1, OE2, OE3, OE4)  
CS PD1  
Table 4.  
Parameter  
Min Typ Max  
Unit Test Conditions/Comments  
Specifications apply to the  
LOGIC INPUTS ( in OTP  
CS  
pin while in OTP programming mode  
CS  
FUNCTION)  
See VPROG definition in Tabl e 1; OTP programming must be done  
with VDD = 3.3 V  
Input Voltage (VPROG  
)
5.25 5.5  
VDD + 2.5  
V
Input Current  
20  
25  
mA  
µs  
Current consumed during OTP programming  
Time required per bit programmed  
Time to OTP Program  
LOGIC INPUTS ( ,OEREF, OE1,  
800  
Numbers are valid for VDD = 2.5 V and 3.3 V  
PD1  
OE2, OE3, OE4,  
Input Voltage  
High (VIH)  
)
CS  
2.2  
V
Low (VIL)  
0.8  
60  
V
Input Current (IINH, IINL  
)
38  
3
µA  
pF  
Input Capacitance (CIN)  
REFERENCE INPUTS (XO1, XO2, XO3,XO4)  
Table 5.  
Parameter  
Min Typ Max  
Unit  
Test Conditions/Comments  
REFERENCE INPUT DRIVEN BY  
CRYSTAL RESONATOR  
Crystal Resonator  
Frequency Range  
20  
60  
MHz  
Fundamental mode, AT cut crystal  
Crystal Motional Resistance  
REFERENCE INPUT DRIVEN BY  
A DIFFERENTIAL CLOCK  
100  
Guaranteed by design  
This input is a source follower and must be either dc-coupled 1.8 V  
LVCMO S on the XO2 or XO4 pin, or ac-coupled  
Input Frequency Range  
20  
60  
MHz  
Assumes ac-coupled LVDS (494 mV p-p across the differential pair)  
Minimum limit imposed for jitter performance  
Input Slew Rate  
Differential Input Voltage  
Sensitivity  
133  
250  
V/μs  
Minimum voltage across pins required to ensure switching between  
logic states; the instantaneous voltage on either pin must not  
exceed the supply rails; can accommodate single-ended input by ac  
grounding of complementary input  
mV p-p  
REFERENCE INPUT DRIVEN BY  
A SINGLE-ENDED CLOCK  
The XO2 pin (for PLL1) and XO4 pin (for PLL2) input accepts dc-  
coupled 1.8 V LVCMOS  
Input Frequency Range  
20  
67  
60  
MHz  
V/μs  
DC-coupled  
Input Slew Rate  
Single-Ended Input (XO2,  
XO4 Pins Only)  
Minimum limit imposed for jitter performance  
Input Voltage  
High (VIH)  
Low (VIL)  
V
V
1.48  
0.98  
Rev. B | Page 5 of 44  
 

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