Datasheet > AD9574BCPZ

AD9574BCPZ

更新时间： 2022-02-26 12:14:43

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
35页	873K
描述
Ethernet/Gigabit Ethernet Clock Generator

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中文翻译

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数据手册
替代型号

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AD9574BCPZ 数据手册

AD9574

Data Sheet

MONITOR CLOCK INPUTS (MCLK_x)—DYNAMIC

Typical is given for V_S= 3.3 V 10%, T_A= 25°C, unless otherwise noted. Minimum and maximum values are given over full V_Sand T_A

(−40°C to +85°C) variation.

Table 9.

Parameter

Min Typ Max Unit

Test Conditions/Comments

DIFFERENTIAL INPUT MODE

Input Sensitivity

100

mV p-p

Minimum Input Slew Rate

Duty Cycle

V/µs

Ensures proper device function when using a sinusoidal source

SINGLE-ENDED INPUT CMOS MODE

Duty Cycle

REFERENCE INPUTS (REF0_x AND REF1_x)—STATIC

Typical is given for V_S= 3.3 V 10%, T_A= 25°C, unless otherwise noted. Minimum and maximum values are given over full V_Sand T_A

(−40°C to +85°C) variation.

Table 10.

Parameter

Min

Typ

Max Unit Test Conditions/Comments

DIFFERENTIAL INPUT MODE

Common-Mode Internally Generated

Bias Voltage

1.218

Common-Mode Voltage Tolerance

0.650

1.8

The acceptable common-mode range for a 200 mV p-p

dc-coupled input signal

Differential Input Capacitance

Differential Input Resistance

SINGLE-ENDED INPUT CMOS MODE

Hysteresis

4.3

kΩ

220

MΩ

Input Resistance

Input Capacitance

Input High Voltage

Input Low Voltage

1.2

REFERENCE INPUTS (REF0_x AND REF1_x)—DYNAMIC

Typical is given for V_S= 3.3 V 10%, T_A= 25°C, unless otherwise noted. Minimum and maximum values are given over full V_Sand T_A

(−40°C to +85°C) variation.

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL INPUT MODE

Input Sensitivity

200

100

mV p-p

V/µs

Minimum Input Slew Rate

Minimum limit imposed for jitter performance (when using a

sinusoidal source, for example)

Duty Cycle

PLL ×2 Multiplier Bypass

PLL ×2 Multiplier Active

OUT0 ×2 Multiplier Active

SINGLE-ENDED INPUT CMOS MODE

Duty Cycle

PLL ×2 Multiplier Bypass

PLL ×2 Multiplier Active

OUT0 ×2 Multiplier Active

Ensures OUT0_x duty cycle limits with OUT0 ×2 multiplier

enabled

Rev. B | Page 8 of 35

1...5 6 789 10 11...35

中文翻译

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AD9574BCPZ 替代型号

型号	品牌	替代类型	描述	数据表
AD9574BCPZ	ADI	当前型号	Ethernet/Gigabit Ethernet Clock Generator
AD9574BCPZ-REEL7	ADI	完全替代	Ethernet/Gigabit Ethernet Clock Generator

与AD9574BCPZ相关器件

型号	品牌	获取价格	描述	数据表
AD9574BCPZ-REEL7	ADI	获取价格	Ethernet/Gigabit Ethernet Clock Generator
AD9575	ADI	获取价格	Network Clock Generator, Two Outputs
AD9575ARUZLVD	ADI	获取价格	Network Clock Generator, Two Outputs
AD9575ARUZPEC	ADI	获取价格	Network Clock Generator, Two Outputs
AD9575-EVALZ-LVD	ADI	获取价格	Network Clock Generator, Two Outputs
AD9575-EVALZ-PEC	ADI	获取价格	Network Clock Generator, Two Outputs
AD9576	ADI	获取价格	Dual PLL, Asynchronous Clock Generator
AD9576BCPZ	ADI	获取价格	Dual PLL, Asynchronous Clock Generator
AD9576BCPZ-REEL7	ADI	获取价格	Dual PLL, Asynchronous Clock Generator
AD9577	ADI	获取价格	Clock Generator with Dual PLLs

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