Datasheet > AD9574BCPZ

AD9574BCPZ

更新时间： 2022-02-26 12:14:43

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
35页	873K
描述
Ethernet/Gigabit Ethernet Clock Generator

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数据手册

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AD9574BCPZ 数据手册

Data Sheet

AD9574

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVDS (OUT4_x TO OUT6_x ONLY )

OUT4_x, OUT5_x

Output Rise Time, t_RL

Output Fall Time, t_FL

OUT6_x

100 Ω termination (differential)

151

152

193

195

238

242

Measured differentially

Output Rise Time, t_RL

Output Fall Time, t_FL

Duty Cycle

221

224

242

241

273

270

Measured differentially

OUT4_x, OUT5_x

OUT6_x

1.8 V CMOS (OUT6_x ONLY )

Output Rise Time, t_RC

Output Fall Time, t_FC

Duty Cycle

C_LOAD= 10 pF

1.2

1.7

1.8

3.3 V CMOS (OUT0_x, OUT1_x, AND

OUT6_x ONLY )

C_LOAD= 10 pF

Output Rise Time, t_RC

Output Fall Time, t_FC

Duty Cycle

0.5

0.6

1.0

1.1

OUT0_x

Not applicable for 38.88 MHz and 50 MHz

operation

OUT1_x

OUT6_x

MONITOR CLOCK INPUTS (MCLK_x)—STATIC

Typical is given for V_S= 3.3 V 10%, T_A= 25°C, unless otherwise noted. Minimum and maximum values are given over full V_Sand T_A

(−40°C to +85°C) variation.

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL INPUT MODE

Common-Mode Internally Generated Bias

Voltage

1.192

Common-Mode Voltage Tolerance

0.6

1.5

The acceptable common-mode range for a

200 mV p-p dc-coupled input signal

Differential Input Capacitance

Differential Input Resistance

SINGLE-ENDED INPUT CMOS MODE

Hysteresis

kΩ

230

MΩ

Input Resistance

Input Capacitance

Input High Voltage

Input Low Voltage

1.2

Rev. B | Page 7 of 35

1...4 5 678 9 10...35

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