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AD9572ACPZLVD-RL PDF预览

AD9572ACPZLVD-RL

更新时间: 2024-01-23 02:52:38
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器光纤以太网
页数 文件大小 规格书
20页 410K
描述
Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

AD9572ACPZLVD-RL 数据手册

 浏览型号AD9572ACPZLVD-RL的Datasheet PDF文件第11页浏览型号AD9572ACPZLVD-RL的Datasheet PDF文件第12页浏览型号AD9572ACPZLVD-RL的Datasheet PDF文件第13页浏览型号AD9572ACPZLVD-RL的Datasheet PDF文件第15页浏览型号AD9572ACPZLVD-RL的Datasheet PDF文件第16页浏览型号AD9572ACPZLVD-RL的Datasheet PDF文件第17页 
AD9572  
THEORY OF OPERATION  
REFSEL  
BYPASS1  
VS  
GND  
VS  
XTAL  
OSC  
CMOS  
1
0
25M  
REFCLK  
LDO  
PHASE  
DIVIDE  
BY 17  
FREQUENCY  
DETECTOR  
106.25MHz  
106M  
106M  
CHARGE  
PUMP  
DIVIDE  
BY 5  
DIVIDE  
BY 4  
LVPECL/  
LVDS  
106M  
106M  
VCO  
LDO  
V
LDO  
BYPASS2  
PHASE  
FREQUENCY  
DETECTOR  
DIVIDE  
BY 25  
156.25MHz  
156M  
156M  
CHARGE  
PUMP  
DIVIDE  
BY 4  
DIVIDE  
BY 4  
LVPECL/  
LVDS  
VCO  
125MHz/100MHz  
V
LDO  
0
1
DIVIDE  
BY 5  
DIVIDE  
BY 4  
100M/125M  
100M/125M  
LVPECL/  
LVDS  
LEVEL  
DECODE  
FREQSEL  
125MHz/100MHz  
0
1
100M/125M  
100M/125M  
DIVIDE  
BY 5  
LVPECL/  
LVDS  
33.33MHz  
CMOS  
DIVIDE  
BY 3  
AD9572  
33M  
FORCE_LOW  
Figure 12. Detailed Block Diagram  
Figure 12 shows a block diagram of the AD9572. The chip  
combines dual PLL cores, which are configured to generate the  
specific clock frequencies required for networking applications,  
without any user programming. This PLL is based on proven  
Analog Devices synthesizer technology, noted for its exceptional  
phase noise performance. The AD9572 is highly integrated and  
includes loop filters, regulators for supply noise immunity, all  
the necessary dividers with multiple output buffers in a choice  
of formats, and a crystal oscillator. A user need only supply a  
25 MHz reference clock or an external crystal to implement an  
entire line card clocking solution  
OUTPUTS  
Table 14 provides a summary of the outputs available.  
Table 14. Output Formats  
Frequency  
25 MHz  
106.25 MHz  
156.25 MHz  
100 MHz or 125 MHz  
33.33 MHz  
Format  
Copies  
CMOS  
1
2
1
2
1
LVPECL/LVDS  
LVPECL/LVDS  
LVPECL/LVDS  
CMOS  
Note that the pins labeled 100M/125M can provide 100 MHz or  
125 MHz by strapping the FREQSEL pin as shown in Table 15.  
that does not require any processor intervention. A copy of  
the 25 MHz reference source is also available.  
Rev. 0 | Page 14 of 20  
 
 
 

AD9572ACPZLVD-RL 替代型号

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AD9572ACPZLVD-RL ADI

当前型号

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs
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完全替代

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

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