Datasheet > AD9573

AD9573

更新时间： 2024-02-29 16:14:49

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器 PC
页数	文件大小	规格书
12页	279K
描述
PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs

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AD9573 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	TSSOP, TSSOP16,.25	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.47
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	1
端子数量：	16	最高工作温度：	85 °C
最低工作温度：	-40 °C	最大输出时钟频率：	100 MHz
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装等效代码：	TSSOP16,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3 V	主时钟/晶体标称频率：	25 MHz
认证状态：	Not Qualified	座面最大高度：	1.2 mm
子类别：	Clock Generators	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	4.4 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

AD9573 数据手册

PCI-Express Clock Generator IC,

PLL Core, Dividers, Two Outputs

AD9573

FEATURES

GENERAL DESCRIPTION

Fully integrated VCO/PLL core

0.54 ps rms jitter from 12 kHz to 20 MHz

Input crystal frequency of 25 MHz

Preset divide ratios for 100 MHz, 33.33 MHz

LVDS/LVCMOS output format

Integrated loop filter

Space saving 4.4 mm × 5.0 mm TSSOP

0.235 W power dissipation

3.3 V operation

The AD9573 provides a highly integrated, dual output clock

generator function including an on-chip PLL core that is

optimized for PCI-e applications. The integer-N PLL design

is based on the Analog Devices, Inc., proven portfolio of high

performance, low jitter frequency synthesizers to maximize line

card performance. Other applications with demanding phase

noise and jitter requirements also benefit from this part.

The PLL section consists of a low noise phase frequency

detector (PFD), a precision charge pump, a low phase noise

voltage controlled oscillator (VCO), and a preprogrammed

feedback divider and output divider.

APPLICATIONS

Line cards, switches, and routers

CPU/PCIe applications

Low jitter, low phase noise clock generation

By connecting an external 25 MHz crystal, output frequencies

of 100 MHz and 33.33 MHz can be locked to the input reference.

The output divider and feedback divider ratios are prepro-

grammed for the required output rates. No external loop filter

components are required, thus conserving valuable design time

and board space.

The AD9573 is available in a 16-lead 4.4 mm × 5.0 mm TSSOP

and can be operated from a single 3.3 V supply. The temperature

range is −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

VDD × 5

LDO

VCO

LVDS

100MHz

XTAL

OSC

LVCMOS

33.33MHz

AD9573

GND × 5

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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