Datasheet > AD9554

AD9554

更新时间： 2024-01-24 11:35:01

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
116页	1064K
描述
Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

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AD9554 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN,
针数：	72	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	2.31	Is Samacsys：	N
JESD-30 代码：	S-XQCC-N72	JESD-609代码：	e3
长度：	10 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	72
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	座面最大高度：	1 mm
标称供电电压：	1.5 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	10 mm
Base Number Matches：	1

AD9554 数据手册

Data Sheet

AD9554

DISTRIBUTION CLOCK OUTPUTS

Table 8.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

14 mA (HCSL-, LVDS-COMPATIBLE) MODE

Unless otherwise stated, specifications dc-

coupled with no output termination resistor;

when ac-coupled, LVDS-compatible amplitudes are

achieved with a 100 Ω resistor across the output

pair; HCSL-compatible amplitudes achieved with

no termination resistor across the output pair;

output current setting: 14 mA

Output Frequency

0.430

941

781

MHz

Frequency range all four PLLs can generate using

unique VCO frequencies; frequencies outside this

range are possible on some of the PLLs, but can

result in increased VCO coupling due to multiple

PLLs using the same VCO frequency

Continuous Output Frequency Range

Maximum Output Frequency

All four PLLs can generate this range at the same

time while using unique VCO frequencies

PLL0 to PLL3 Using Unique VCO

Frequencies

PLL0, PLL1, and PLL2

941

MHz

Maximum frequency all four PLLs can generate

using unique VCO frequencies

Limited by 1250 MHz maximum input frequency

to channel divider (Q divider)

1250

PLL3

1187

125

MHz

Limited by 4748 MHz maximum VCO frequency

Rise/Fall Time (20% to 80%)¹

Duty Cycle

190

Up to f_OUT= 750 MHz

Up to f_OUT= 941 MHz

Up to f_OUT= 1250 MHz

Differential Output Voltage Swing

Differential voltage swing between output pins;

measured with output driver static; peak-to-peak

differential output amplitude 2× this level with

driver toggling; see Figure 11 for output

amplitude vs. output frequency

Without 100 Ω Termination Resistor

With 100 Ω Termination Resistor Across

Outputs

635

294

840

390

1000

463

Common-Mode Output Voltage

Reference Input-to-Output Delay Variation

over Temperature

310

420

600

525

fs/°C

Output driver static; no termination resistor

DPLL locked to same input reference at all times;

stable system clock source (noncrystal)

Static Phase Offset Variation from Active

Reference to Output over Voltage

Extremes

fs/mV

21 mA MODE

Unless otherwise stated, specifications

dc-coupled with 50 Ω output termination resistor to

ground; output current setting = 21 mA

Output Frequency

0.430

941

781

MHz

Frequency range all four PLLs can generate using

unique VCO frequencies; frequencies outside this

range are possible on some of the PLLs, but can

result in increased VCO coupling due to multiple

PLLs using the same VCO frequency

Continuous Output Frequency Range

Maximum Output Frequency

All four PLLs can generate this range at the same

time while using unique VCO frequencies

PLL0 to PLL3 Using Unique VCO

Frequencies

PLL0, PLL1, and PLL2

941

MHz

Maximum frequency all four PLLs can generate

using unique VCO frequencies

Limited by 1250 MHz maximum input frequency

to channel divider (Q divider)

1250

PLL3

1187

125

MHz

Limited by 4748 MHz maximum VCO frequency

Rise/Fall Time (20% to 80%)¹

190

Rev. D | Page 9 of 116

1...6 7 8910 11 12...116

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与AD9554相关器件

型号	品牌	描述	获取价格	数据表
AD9554-1	ADI	四路PLL、四通道输入、四通道输出多服务线路卡自适应时钟转换器	获取价格
AD9554-1BCPZ	ADI	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator	获取价格
AD9554-1BCPZ-REEL7	ADI	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator	获取价格
AD9554BCPZ	ADI	Quad PLL, Quad Input, 8-output Multiservice Line Card Adaptive Clock Translator	获取价格
AD9554BCPZ-REEL	ADI	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator	获取价格
AD9554BCPZ-REEL7	ADI	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator	获取价格

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