Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> AD9552PCBZ

AD9552PCBZ

更新时间： 2024-02-09 13:41:32

品牌	Logo	应用领域
亚德诺 - ADI		振荡器
页数	文件大小	规格书
32页	477K
描述
Oscillator Frequency Upconverter

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中文翻译

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技术参数
数据手册

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AD9552PCBZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.48
Samacsys Confidence：		Samacsys Status：	Released
Samacsys PartID：	372609	Samacsys Pin Count：	33
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	Other
Samacsys Footprint Name：	QFN50P500X500X100-33N	Samacsys Released Date：	2017-01-11 11:21:59
Is Samacsys：	N	应用程序：	SONET;SDH
JESD-30 代码：	S-XQCC-N32	JESD-609代码：	e3
长度：	5 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装等效代码：	LCC32,.2SQ,20	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1 mm	子类别：	Other Telecom ICs
最大压摆率：	0.169 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	5 mm
Base Number Matches：	1

AD9552PCBZ 数据手册

AD9552

Address Bit

0x18 [7:3]

Bit Name

Description

P₁divider

Bits[4:0] of the 6-bit P₁divider for OUT1 (1 ≤ P₁≤ 63). Do not set these bits to 000000. Default is

P₁= 10 0000 (32). The P₁bits are ineffective unless Register 0x19[7] = 1.

[2:0]

P₀divider

The 3-bit P₀divider for OUT1. The P₀divide value is as follows:

000 = 4 (default).

001 = 5.

010 = 6.

011 = 7.

100 = 8.

101 = 9.

110 = 10.

111 = 11.

The P₀bits are ineffective unless Register 0x19[7] = 1.

0x19

Enable SPI control of

OUT1 dividers

Controls functionality of OUT1 dividers.

0 = OUT1 dividers defined by the Y[5:0] pins (default).

1 = contents of Register 0x17 and Register 0x18 define OUT1 dividers (P₀and P₁).

[6:0]

Unused

Unused.

Input Receiver and Band Gap Control (Register 0x1A)

Table 22.

Address Bit

Bit Name

Description

0x1A

Receiver reset

Input receiver reset control. This is an autoclearing bit.

0 = normal operation (default).

1 = reset input receiver logic.

[6:2] Band gap voltage adjust

Controls the band gap voltage setting from minimum (0 0000) to maximum (1 1111).

Default is 0 0000.

Unused

Unused.

Enable SPI control of band gap

voltage

Enables functionality of Bits[6:2].

0 = the device automatically selects receiver band gap voltage (default).

1 = Bits[6:2] define the receiver band gap voltage.

XTAL Control (Register 0x1B to Register 0x1D)

Table 23.

Address

Bit

Bit Name

Description

0x1B

Disable SPI control of XTAL

tuning capacitance

Disables functionality of Bits[5:0].

0 = tuning capacitance defined by Bits[5:0].

1 = the device automatically selects XTAL tuning capacitance (default).

Unused

Unused.

[5:0] XTAL tuning capacitor control

Capacitance value coded as inverted binary (0.25 pF per bit); that is, 111111 is 0 pF,

111110 is 0.25 pF, and so on. The default value, 000000, is 15.75 pF.

0x1C

0x1D

[7:0] Unused

[7:3] Unused

Unused.

Select 2× frequency multiplier

Select/bypass the 2× frequency multiplier.

0 = bypassed (default).

1 = selected.

Unused

Unused.

Use crystal resonator

Automatic external reference select override.

0 = the device automatically selects the external reference path if an external

reference signal is present (default).

1 = the device uses the crystal resonator input whether or not an external reference

signal is present.

Rev. C | Page 27 of 32

1...24 25 262728 29 30...32

中文翻译

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与AD9552PCBZ相关器件

型号	品牌	获取价格	描述	数据表
AD9553	ADI	获取价格	Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9553/PCBZ	ADI	获取价格	Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9553BCPZ	ADI	获取价格	Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9553BCPZ-REEL7	ADI	获取价格	Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
AD9554	ADI	获取价格	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9554-1	ADI	获取价格	四路PLL、四通道输入、四通道输出多服务线路卡自适应时钟转换器
AD9554-1BCPZ	ADI	获取价格	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9554-1BCPZ-REEL7	ADI	获取价格	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator
AD9554BCPZ	ADI	获取价格	Quad PLL, Quad Input, 8-output Multiservice Line Card Adaptive Clock Translator
AD9554BCPZ-REEL	ADI	获取价格	Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator

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