Datasheet > AD9524

AD9524

更新时间： 2024-02-05 01:40:18

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器
页数	文件大小	规格书
56页	863K
描述
Jitter Cleaner and Clock Generator with 6 Differential or 13 LVCMOS Outputs

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

AD9524 技术参数

Source Url Status Check Date：	2013-05-01 14:56:31.078	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Not Recommended
包装说明：	HVQCCN,	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	7.26
JESD-30 代码：	S-XQCC-N48	JESD-609代码：	e3
长度：	7 mm	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
最大输出时钟频率：	1000 MHz	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	主时钟/晶体标称频率：	250 MHz
座面最大高度：	1 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	7 mm
uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER	Base Number Matches：	1

AD9524 数据手册

Jitter Cleaner and Clock Generator with

6 Differential or 13 LVCMOS Outputs

Data Sheet

AD9524

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Output frequency: <1 MHz to 1 GHz

Start-up frequency accuracy: < 100 ppm (determined by

VCXO reference accuracy)

OSC

REFA,

AD9524

REFA

OUT0,

REFB,

Zero delay operation

PLL1

PLL2

OUT0

Input-to-output edge timing: < 150 ps

6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

6 dedicated output dividers with jitter-free adjustable delay

Adjustable delay: 63 resolution steps of ½ period of VCO

output divider

REFB

OUT1,

OUT1

REF_TEST

SCLK/SCL

SDIO/SDA

SDO

CONTROL

INTERFACE

(SPI AND I C)

OUT4,

OUT4

Output-to-output skew: < 50 ps

ZERO

DELAY

Duty-cycle correction for odd divider settings

Automatic synchronization of all outputs on power-up

Absolute output jitter: <200 fs at 122.88 MHz

Integration range: 12 kHz to 20 MHz

Distribution phase noise floor: −160 dBc/Hz

Digital lock detect

Nonvolatile EEPROM stores configuration settings

SPI- and I²C-compatible serial control port

Dual PLL architecture

OUT5,

OUT5

6-CLOCK

DISTRIBUTION

EEPROM

ZD_IN, ZD_IN

Figure 1.

GENERAL DESCRIPTION

The AD9524 provides a low power, multi-output, clock

PLL1

distribution function with low jitter performance, along with an

on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to

4.0 GHz.

Low bandwidth for reference input clock cleanup with

external VCXO

Phase detector rate of 300 kHz to 75 MHz

Redundant reference inputs

Auto and manual reference switchover modes

Revertive and nonrevertive switching

Loss of reference detection with holdover mode

Low noise LVCMOS output from VCXO used for RF/IF

synthesizers

The AD9524 is defined to support the clock requirements for

long term evolution (LTE) and multicarrier GSM base station

designs. It relies on an external VCXO to provide the reference

jitter cleanup to achieve the restrictive low phase noise require-

ments necessary for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide

both single-ended and differential operation. When connected

to a recovered system reference clock and a VCXO, the device

generates six low noise outputs with a range of 1 MHz to 1 GHz,

and one dedicated buffered output from the input PLL (PLL1).

The frequency and phase of one clock output relative to another

clock output can be varied by means of a divider phase select

function that serves as a jitter-free coarse timing adjustment in

increments that are equal to one-half the period of the signal

coming out of the VCO.

PLL2

Phase detector rate of up to 250 MHz

Integrated low noise VCO

APPLICATIONS

LTE and multicarrier GSM base stations

Wireless and broadband infrastructure

Medical instrumentation

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC,

and other 10 Gbps protocols

An in-package EEPROM can be programmed through the serial

interface to store user defined register settings for power-up and

chip reset.

Forward error correction (G.710)

High performance wireless transceivers

ATE and high performance instrumentation

Rev. D

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

12 3 4 5 6 7...56

下载PDF

与AD9524相关器件

型号	品牌	描述	获取价格	数据表
AD9524BCPZ	ADI	6 Output, Dual Loop Clock Generator	获取价格
AD9524BCPZ-REEL7	ADI	6 Output, Dual Loop Clock Generator	获取价格
AD9525	ADI	Low Jitter Clock Generator with Eight LVPECL Outputs	获取价格
AD9525/PCBZ	ADI	Low Jitter Clock Generator with Eight LVPECL Outputs	获取价格
AD9525/PCBZ-VCO	ADI	Low Jitter Clock Generator with Eight LVPECL Outputs	获取价格
AD9525BCPZ	ADI	Low Jitter Clock Generator with Eight LVPECL Outputs	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

AD9524

AD9524 技术参数

AD9524 数据手册

与AD9524相关器件

与AD9524相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AD9524

AD9524 技术参数

AD9524 数据手册

与AD9524相关器件

与AD9524相关文章

您还可以找

您在本页遇到什么问题？