AD9518-1A-PCBZ

更新时间： 2024-01-28 12:09:01

品牌	Logo	应用领域
亚德诺 - ADI		时钟发生器
页数	文件大小	规格书
64页	1090K
描述
6-Output Clock Generator with Integrated 2.5 GHz VCO

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AD9518-1A-PCBZ 技术参数

生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	48
Reach Compliance Code：	unknown	风险等级：	5.68
系列：	9518	输入调节：	DIFFERENTIAL MUX
JESD-30 代码：	S-XQCC-N48	长度：	7 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	48
实输出次数：	6	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	传播延迟（tpd）：	1.18 ns
认证状态：	COMMERCIAL	Same Edge Skew-Max（tskwd）：	0.22 ns
座面最大高度：	1 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	NOT SPECIFIED	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	7 mm	最小 fmax：	2950 MHz
Base Number Matches：	1

AD9518-1A-PCBZ 数据手册

AD9518-1

Data Sheet

CLOCK INPUTS

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CLOCK INPUTS (CLK, CLK)

Input Frequency

Differential input

0¹

2.4

1.6

GHz

High frequency distribution (VCO divider)

Distribution only (VCO divider bypassed)

Input Sensitivity, Differential

Input Level, Differential

150

mV p-p

Measured at 2.4 GHz; jitter performance is

improved with slew rates > 1 V/ns

Larger voltage swings may turn on the protection

diodes and may degrade jitter performance

V p-p

Input Common-Mode Voltage, V_CM

Input Common-Mode Range, V_CMR

Input Sensitivity, Single-Ended

Input Resistance

1.3

1.57

1.8

Self-biased; enables ac coupling

With 200 mV p-p signal applied; dc-coupled

CLK ac-coupled; CLK ac-bypassed to RF ground

Self-biased

150

4.7

mV p-p

kΩ

3.9

5.7

Input Capacitance

¹Below about 1 MHz, the input should be dc-coupled. Care should be taken to match V_CM

CLOCK OUTPUTS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Termination = 50 Ω to V_S− 2 V

Differential (OUT, OUT)

LVPECL CLOCK OUTPUTS

OUT0, OUT1, OUT2, OUT3, OUT4, OUT5

Output Frequency, Maximum

2950

MHz

Using direct to output; see Figure 16 for peak-to-peak

differential amplitude

V_{S_LVPECL}

1.12

V_{S_LVPECL}

2.03

−

V_{S_LVPECL}

0.98

V_{S_LVPECL}

1.77

−

V_{S_LVPECL}

0.84

V_{S_LVPECL}

1.49

−

Output High Voltage (V_OH

)

Output Low Voltage (V_OL

)

This is V_OH− V_OLfor each leg of a differential pair for

default amplitude setting with driver not toggling; the

peak-to-peak amplitude measured using a differential

probe across the differential pair with the driver toggling

is roughly 2× these values (see Figure 16 for variation

over frequency)

Output Differential Voltage (V_OD

)

550

790

980

TIMING CHARACTERISTICS

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL

Output Rise Time, t_RP

Output Fall Time, t_FP

Termination = 50 Ω to V_S− 2 V; level = 810 mV

20% to 80%, measured differentially

80% to 20%, measured differentially

180

PROPAGATION DELAY, t_PECL, CLK-TO-LVPECL

OUTPUT

High Frequency Clock Distribution

Configuration

Clock Distribution Configuration

Variation with Temperature

835

773

995

1180

1090

See Figure 28

See Figure 30

933

0.8

ps/°C

OUTPUT SKEW, LVPECL OUTPUTS¹

LVPECL Outputs That Share the Same

Divider

LVPECL Outputs on Different Dividers

All LVPECL Outputs Across Multiple Parts

220

¹This is the difference between any two similar delay paths while operating at the same voltage and temperature.

Rev. C | Page 6 of 64

1...3 4 567 8 9...64

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AD9518-1BCPZ	ADI	6-Output Clock Generator with Integrated 2.5 GHz VCO	获取价格
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AD9518-2BCPZ	ROCHESTER	9518 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC48, 7 X 7	获取价格

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