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AD9518-1A-PCBZ PDF预览

AD9518-1A-PCBZ

更新时间： 2024-01-09 09:17:36
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
64页 1090K
描述
6-Output Clock Generator with Integrated 2.5 GHz VCO

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AD9518-1A-PCBZ 技术参数

生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：48
Reach Compliance Code：unknown风险等级：5.68
系列：9518输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N48长度：7 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：48
实输出次数：6最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE传播延迟（tpd）：1.18 ns
认证状态：COMMERCIALSame Edge Skew-Max（tskwd）：0.22 ns
座面最大高度：1 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：NOT SPECIFIED端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：7 mm最小 fmax：2950 MHz
Base Number Matches：1

AD9518-1A-PCBZ 数据手册

 浏览型号AD9518-1A-PCBZ的Datasheet PDF文件第2页浏览型号AD9518-1A-PCBZ的Datasheet PDF文件第3页浏览型号AD9518-1A-PCBZ的Datasheet PDF文件第4页浏览型号AD9518-1A-PCBZ的Datasheet PDF文件第6页浏览型号AD9518-1A-PCBZ的Datasheet PDF文件第7页浏览型号AD9518-1A-PCBZ的Datasheet PDF文件第8页 
Data Sheet  
AD9518-1  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
CHARGE PUMP (CP)  
ICP Sink/Source  
CPV is CP pin voltage; VCP is charge pump power supply voltage  
Programmable  
High Value  
Low Value  
4.8  
0.60  
2.5  
2.7/10  
1
2
1.5  
2
mA  
mA  
%
kΩ  
nA  
%
With CPRSET = 5.1 kΩ  
Absolute Accuracy  
CPRSET Range  
ICP High Impedance Mode Leakage  
Sink-and-Source Current Matching  
ICP vs. CPV  
ICP vs. Temperature  
PRESCALER (PART OF N DIVIDER)  
Prescaler Input Frequency  
P = 1 FD  
CPV = VCP/2 V  
0.5 < CPV < VCP − 0.5 V  
0.5 < CPV < VCP − 0.5 V  
CPV = VCP/2 V  
%
%
See the VCXO/VCO Feedback Divider N—P, A, B, R section  
300  
600  
900  
200  
1000  
2400  
3000  
3000  
300  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
P = 2 FD  
P = 3 FD  
P = 2 DM (2/3)  
P = 4 DM (4/5)  
P = 8 DM (8/9)  
P = 16 DM (16/17)  
P = 32 DM (32/33)  
Prescaler Output Frequency  
A, B counter input frequency (prescaler input frequency divided  
by P)  
PLL DIVIDER DELAYS  
Register 0x019: R, Bits[5:3]; N, Bits[2:0] (see Table 44)  
000  
001  
010  
011  
100  
101  
110  
111  
Off  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
ps  
330  
440  
550  
660  
770  
880  
990  
NOISE CHARACTERISTICS  
In-Band Phase Noise of the Charge  
Pump/Phase Frequency Detector  
(In-Band Is Within the LBW of the PLL)  
The PLL in-band phase noise floor is estimated by measuring the  
in-band phase noise at the output of the VCO and subtracting  
20 log(N) (where N is the value of the N divider)  
At 500 kHz PFD Frequency  
At 1 MHz PFD Frequency  
At 10 MHz PFD Frequency  
At 50 MHz PFD Frequency  
PLL Figure of Merit (FOM)  
−165  
−162  
−151  
−143  
−220  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz Reference slew rate > 0.25 V/ns; FOM + 10 log(fPFD) is an approxi-  
mation of the PFD/CP in-band phase noise (in the flat region) inside  
the PLL loop bandwidth; when running closed-loop, the phase  
noise, as observed at the VCO output, is increased by 20 log(N)  
PLL DIGITAL LOCK DETECT WINDOW2  
Signal available at LD, STATUS, and REFMON pins  
when selected by appropriate register settings  
Required to Lock (Coincidence of Edges)  
Low Range (ABP 1.3 ns, 2.9 ns)  
High Range (ABP 1.3 ns, 2.9 ns)  
High Range (ABP 6.0 ns)  
Selected by Register 0x017[1:0] and Register 0x018[4]  
3.5  
7.5  
3.5  
ns  
ns  
ns  
Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b  
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b  
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b  
To Unlock After Lock (Hysteresis)2  
Low Range (ABP 1.3 ns, 2.9 ns)  
High Range (ABP 1.3 ns, 2.9 ns)  
High Range (ABP 6.0 ns)  
7
15  
11  
ns  
ns  
ns  
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b  
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b  
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b  
1
REFIN  
REFIN and  
self-bias points are offset slightly to avoid chatter on an open input condition.  
2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.  
Rev. C | Page 5 of 64  
12345678...64

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