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AD9518-1A-PCBZ

更新时间： 2024-01-29 02:48:51
品牌 Logo 应用领域
亚德诺 - ADI 时钟发生器
页数 文件大小 规格书
64页 1090K
描述
6-Output Clock Generator with Integrated 2.5 GHz VCO

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AD9518-1A-PCBZ 技术参数

生命周期：Active零件包装代码：QFN
包装说明：HVQCCN,针数：48
Reach Compliance Code：unknown风险等级：5.68
系列：9518输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N48长度：7 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：48
实输出次数：6最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE传播延迟（tpd）：1.18 ns
认证状态：COMMERCIALSame Edge Skew-Max（tskwd）：0.22 ns
座面最大高度：1 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：NOT SPECIFIED端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：7 mm最小 fmax：2950 MHz
Base Number Matches：1

AD9518-1A-PCBZ 数据手册

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AD9518-1  
Data Sheet  
SPECIFICATIONS  
Typical values are given for VS = VS_LVPECL = 3.3 V 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.  
Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation.  
POWER SUPPLY REQUIREMENTS  
Table 1.  
Parameter  
Min  
Typ  
Max  
3.465  
VS  
Unit  
V
V
V
kΩ  
kΩ  
Test Conditions/Comments  
3.3 V 5%  
Nominally 2.5 V to 3.3 V 5%  
Nominally 3.3 V to 5.0 V 5%  
Sets internal biasing currents; connect to ground  
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA);  
actual current can be calculated by CP_lsb = 3.06/CPRSET;  
connect to ground  
VS  
VS_LVPECL  
VCP  
RSET Pin Resistor  
CPRSET Pin Resistor  
3.135 3.3  
2.375  
VS  
5.25  
4.12  
5.1  
2.7  
10  
BYPASS Pin Capacitor  
220  
nF  
Bypass for internal LDO regulator; necessary for LDO stability;  
connect to ground  
PLL CHARACTERISTICS  
Table 2.  
Parameter  
Min  
2300  
0.5  
Typ  
Max  
Unit  
Test Conditions/Comments  
VCO (ON-CHIP)  
Frequency Range  
VCO Gain (KVCO  
2650  
MHz  
MHz/V  
V
See Figure 11  
See Figure 6  
)
50  
Tuning Voltage (VT)  
VCP − 0.5  
VCP ≤ VS when using internal VCO; outside of this range, the CP  
spurs may increase due to CP up/down mismatch  
Frequency Pushing (Open-Loop)  
Phase Noise at 100 kHz Offset  
Phase Noise at 1 MHz Offset  
REFERENCE INPUTS  
1
MHz/V  
dBc/Hz f = 2475 MHz  
dBc/Hz f = 2475 MHz  
−105  
−124  
Differential mode (can accommodate single-ended input by  
Differential Mode (REFIN, REFIN)  
ac grounding undriven input)  
Input Frequency  
Input Sensitivity  
0
250  
MHz  
Frequencies below about 1 MHz should be dc-coupled; be careful  
to match VCM (self-bias voltage)  
250  
mV p-p PLL figure of merit (FOM) increases with increasing slew rate  
(see Figure 10); the input sensitivity is sufficient for ac-coupled  
LVPECL and LVDS signals  
V
V
Self-Bias Voltage, REFIN  
Self-Bias Voltage, REFIN  
Input Resistance, REFIN  
Input Resistance, REFIN  
Dual Single-Ended Mode (REF1, REF2)  
Input Frequency (AC-Coupled)  
Input Frequency (DC-Coupled)  
Input Sensitivity (AC-Coupled)  
Input Logic High  
1.35  
1.30  
1.60  
1.50  
1.75  
1.60  
Self-bias voltage of REFIN1  
Self-bias voltage of REFIN1  
Self-biased1  
4.0  
4.4  
4.8  
5.3  
5.9  
6.4  
kΩ  
kΩ  
Self-biased1  
Two single-ended CMOS-compatible inputs  
Slew rate > 50 V/µs  
Slew rate > 50 V/µs; CMOS levels  
Should not exceed VS p-p  
20  
0
250  
250  
MHz  
MHz  
V p-p  
V
0.8  
2.0  
Input Logic Low  
0.8  
V
Input Current  
Pulse Width High/Low  
−100  
1.8  
+100  
µA  
ns  
This value determines the allowable input duty cycle and is the  
amount of time that a square wave is high/low  
Input Capacitance  
2
pF  
Each pin, REFIN/REFIN (REF1/REF2)  
PHASE/FREQUENCY DETECTOR (PFD)  
PFD Input Frequency  
100  
45  
MHz  
MHz  
ns  
ns  
ns  
Antibacklash pulse width = 1.3 ns, 2.9 ns  
Antibacklash pulse width = 6.0 ns  
Register 0x017[1:0] = 01b  
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b  
Register 0x017[1:0] = 10b  
Antibacklash Pulse Width  
1.3  
2.9  
6.0  
Rev. C | Page 4 of 64  
 
 
 
 
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