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AD9510BCPZ-REEL7 PDF预览

AD9510BCPZ-REEL7

更新时间： 2024-02-25 03:45:31
品牌 Logo 应用领域
亚德诺 - ADI 时钟
页数 文件大小 规格书
60页 589K
描述
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

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AD9510BCPZ-REEL7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC64,.35SQ,20针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.34
系列：9510输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N64JESD-609代码：e3
长度：9 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：64
实输出次数：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC64,.35SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：0.695 ns传播延迟（tpd）：1.76 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：1.43 ns
座面最大高度：1 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：40宽度：9 mm
最小 fmax：1200 MHz

AD9510BCPZ-REEL7 数据手册

 浏览型号AD9510BCPZ-REEL7的Datasheet PDF文件第2页浏览型号AD9510BCPZ-REEL7的Datasheet PDF文件第3页浏览型号AD9510BCPZ-REEL7的Datasheet PDF文件第4页浏览型号AD9510BCPZ-REEL7的Datasheet PDF文件第6页浏览型号AD9510BCPZ-REEL7的Datasheet PDF文件第7页浏览型号AD9510BCPZ-REEL7的Datasheet PDF文件第8页 
AD9510  
Parameter  
Min Typ  
Max  
Unit  
Test Conditions/Comments  
NOISE CHARACTERISTICS  
In-Band Noise of the Charge Pump/  
Phase Frequency Detector (In-Band  
Means Within the LBW of the PLL)  
The synthesizer phase noise floor is  
estimated by measuring the in-band  
phase noise at the output of the VCO and  
subtracting 20logN (where N is the  
N divider value).  
@ 50 kHz PFD Frequency  
@ 2 MHz PFD Frequency  
@ 10 MHz PFD Frequency  
@ 50 MHz PFD Frequency  
PLL Figure of Merit  
−172  
−156  
−149  
−142  
−218 +  
10 × log (fPFD  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Approximation of the PFD/CP phase noise  
floor (in the flat region) inside the PLL loop  
bandwidth. When running closed loop this  
phase noise is gained up by 20 × log(N)3.  
)
PLL DIGITAL LOCK DETECT WINDOW4  
Signal available at STATUS pin  
when selected by 08h<5:2>.  
Required to Lock  
Selected by Register ODh.  
(Coincidence of Edges)  
Low Range (ABP 1.3 ns, 2.9 ns)  
High Range (ABP 1.3 ns, 2.9 ns)  
High Range (ABP 6 ns)  
3.5  
7.5  
3.5  
ns  
ns  
ns  
<5> = 1b.  
<5> = 0b.  
<5> = 0b.  
To Unlock After Lock (Hysteresis)4  
Low Range (ABP 1.3 ns, 2.9 ns)  
High Range (ABP 1.3 ns, 2.9 ns)  
High Range (ABP 6 ns)  
Selected by Register ODh.  
<5> = 1b.  
<5> = 0b.  
7
15  
11  
ns  
ns  
ns  
<5> = 0b.  
1 REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition.  
2 CLK2 is electrically identical to CLK1; the distribution-only input can be used as differential or single-ended input (see the Clock Inputs section).  
3 Example: −218 + 10 × log(fPFD) + 20 × log(N) should give the values for the in-band noise at the VCO output.  
4 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.  
CLOCK INPUTS  
Table 2.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
CLOCK INPUTS (CLK1, CLK2)1  
Input Frequency  
Input Sensitivity  
0
1.6  
GHz  
mV p-p  
1502  
Jitter performance can be improved with higher slew  
rates (greater swing).  
Larger swings turn on the protection diodes and can  
degrade jitter performance.  
Input Level  
23  
V p-p  
Input Common-Mode Voltage, VCM  
Input Common-Mode Range, VCMR  
Input Sensitivity, Single-Ended  
Input Resistance  
1.5  
1.3  
1.6  
1.7  
1.8  
V
V
Self-biased; enables ac coupling.  
With 200 mV p-p signal applied; dc coupled.  
CLK2 ac-coupled; CLK2B ac-bypassed to RF ground.  
Self-biased.  
150  
4.8  
2
mV p-p  
kΩ  
pF  
4.0  
5.6  
Input Capacitance  
1 CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.  
2 With a 50 Ω termination, this is −12.5 dBm.  
3 With a 50 Ω termination, this is +10 dBm.  
Rev. A | Page 5 of 60  
 
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