AD9513

更新时间： 2024-09-27 04:04:23

品牌	Logo	应用领域
亚德诺 - ADI		时钟
页数	文件大小	规格书
28页	608K
描述
800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

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AD9513 数据手册

800 MHz Clock Distribution IC, Dividers,

Delay Adjust, Three Outputs

AD9513

FUNCTIONAL BLOCK DIAGRAM

FEATURES

RSET

GND

1.6 GHz differential clock input

3 programmable dividers

LVDS/CMOS

AD9513

Divide-by in range from1 to 32

Phase select for coarse delay adjust

Three 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 300 fs rms

Time delays up to 11.6 ns

OUT0

/1. . . /32

OUT0B

CLK

OUT1

/1. . . /32

Device configured with 4-level logic pins

Space-saving, 32-lead LFCSP

CLKB

OUT1B

SYNCB

OUT2

APPLICATIONS

/1. . . /32

∆t

OUT2B

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

SETUP LOGIC

VREF

S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Figure 1.

ATE

GENERAL DESCRIPTION

The AD9513 features a three-output clock distribution IC in a

design that emphasizes low jitter and phase noise to maximize

data converter performance. Other applications with

demanding phase noise and jitter requirements also benefit

from this part.

One of the outputs features a delay element with three selectable

full-scale delay values (1.8 ns, 6.0 ns, and 11.6 ns), each with

16 steps of fine adjustment.

The AD9513 does not require an external controller for

operation or setup. The device is programmed by means of

11 pins (S0 to S10) using 4-level logic. The programming pins

are internally biased to ⅓ V_S. The VREF pin provides a level of

⅔ V_S. V_S(3.3 V) and GND (0 V) provide the other two logic levels.

There are three independent clock outputs that can be set to

either LVDS or CMOS levels. These outputs operate to

800 MHz in LVDS mode and to 250 MHz in CMOS mode.

Each output has a programmable divider that can be set to

divide by a selected set of integers ranging from 1 to 32. The

phase of one clock output relative to the other clock output can

be set by means of a divider phase select function that serves as

a coarse timing adjustment.

The AD9513 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9513 is available in a 32-lead LFCSP and operates from

a single 3.3 V supply. The temperature range is −40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

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与AD9513相关器件

型号	品牌	获取价格	描述	数据表
AD9513/PCB	ADI	获取价格	800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9513BCPZ	ADI	获取价格	800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9513BCPZ-REEL7	ADI	获取价格	800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9514	ADI	获取价格	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9514/PCB	ADI	获取价格	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9514BCPZ	ADI	获取价格	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9514BCPZ-REEL7	ADI	获取价格	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9515	ADI	获取价格	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
AD9515/PCB	ADI	获取价格	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
AD9515BCPZ	ADI	获取价格	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

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