Datasheet > AD9508BCPZ

AD9508BCPZ

更新时间： 2022-04-16 11:07:02

品牌	Logo	应用领域
亚德诺 - ADI		时钟
页数	文件大小	规格书
40页	838K
描述
1.65 GHz Clock Fanout Buffer with Output Dividers and Delay Adjust

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AD9508BCPZ 数据手册

AD9508

Data Sheet

Parameter

Symbol

Min

Typ

Max Unit

Test Conditions/Comments

OUTPUT LOGIC SKEW¹

CMOS load = 10 pF and LVDS load = 100 Ω

LVDS Output(s) and HSTL Output(s)

119

700

622

Outputs on the same device; assumes

worst-case output combination

Outputs on the same device; assumes

worst-case output combination

Outputs on the same device; assumes

worst-case output combination

LVDS Output(s) and CMOS Output(s)

HSTL Output(s) and CMOS Output(s)

497

424

¹Output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.

LOGIC INPUTS

Table 4.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

RESET SYNC

, IN_SEL

LOGIC INPUTS

Input Voltage

High

V_IH

V_IL

1.7

2.0

2.5 V supply voltage operation

3.3 V supply voltage operation

2.5 V supply voltage operation

3.3 V supply voltage operation

Low

0.7

0.8

Input Current

Input Capacitance

I_INH, I_INL

C_IN

−300

+100 µA

SERIAL PORT SPECIFICATIONS—SPI MODE

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SCLK has a 200 kΩ internal pull-down resistor

Input Voltage

Logic 1

Logic 0

VDD − 0.4

0.4

Input Current

Logic 1

Logic 0

Input Capacitance

SCLK

−4

−85

µA

Input Voltage

Logic 1

Logic 0

VDD − 0.4

0.4

Input Current

Logic 1

Logic 0

Input Capacitance

SDIO

µA

As Input

Input Voltage

Logic 1

Logic 0

VDD − 0.4

0.4

Input Current

Logic 1

Logic 0

−1

µA

Input Capacitance

Rev. A | Page 6 of 40

1...3 4 567 8 9...40

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